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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This is the main header file for Xilinx HDMI TX core. </p>
<p>HDMI TX core is used for transmitting the incoming video and audio streams. It consists of</p>
<ul>
<li>Transmitter core</li>
<li>AXI4-Stream to Video Bridge</li>
<li>Video Timing Controller and</li>
<li>High-bandwidth Digital Content Protection (HDCP) (Optional).</li>
</ul>
<p>The HDMI TX uses three AXI interfaces for Video, Audio and Processor:</p>
<ul>
<li>AXI4-Stream interface for Video, can be single, dual or quad pixels per clock and supports 8 and 10 bits per component.</li>
<li>AXI4-Stream interface for Audio, accepts multiple channels uncompressed and compressed audio data.</li>
<li>AXI4-Lite interface for processor, controls the transmitter. Please do refer AXI Reference Guide (UG761) for more information on AXI interfaces.</li>
</ul>
<p>Transmitter core performs following operations:</p>
<ul>
<li>Converts video data from the video clock domain into the link clock domain.</li>
<li>TMDS (Transition Minimized Differential Signaling) encoding.</li>
<li>Merges encoded video data and packet data into a single HDMI stream.</li>
<li>Optional HDMI stream is encrypted by an external HDCP module.</li>
<li>Over samples HDMI stream if stream bandwidth is too low for the transceiver to handle.</li>
<li>Scrambles encrypted/HDMI stream if data rate is above 3.4 Gbps otherwise bypasses the Scrambler.</li>
</ul>
<p>AXI Video Bridge converts the incoming video AXI-stream to native video.</p>
<p>Video Timing Controller (VTC) generates the native video timing.</p>
<p><b>Core Features </b></p>
<p>For a full description of HDMI TX features, please see the hardware specification.</p>
<p><b>Software Initialization &amp; Configuration</b></p>
<p>The application needs to do following steps in order for preparing the HDMI TX core to be ready.</p>
<ul>
<li>Call XV_HdmiTx1_LookupConfig using a device ID to find the core configuration.</li>
<li>Call XV_HdmiTx1_CfgInitialize to initialize the device and the driver instance associated with it.</li>
</ul>
<p><b>Interrupts </b></p>
<p>This driver provides interrupt handlers</p>
<ul>
<li>XV_HdmiTx1_IntrHandler, for handling the interrupts from the HDMI TX core PIO and DDC peripheral respectively.</li>
</ul>
<p>Application developer needs to register interrupt handler with the processor, within their examples. Whenever processor calls registered application's interrupt handler associated with interrupt id, application's interrupt handler needs to call appropriate peripheral interrupt handler reading peripheral's Status register.</p>
<p>This driver provides XV_HdmiTx1_SetCallback API to register functions with HDMI TX core instance.</p>
<p><b> Virtual Memory </b></p>
<p>This driver supports Virtual Memory. The RTOS is responsible for calculating the correct device base address in Virtual Memory space.</p>
<p><b> Threads </b></p>
<p>This driver is not thread safe. Any needs for threads or thread mutual exclusion must be satisfied by the layer above this driver.</p>
<p><b> Asserts </b></p>
<p>Asserts are used within all Xilinx drivers to enforce constraints on argument values. Asserts can be turned off on a system-wide basis by defining at compile time, the NDEBUG identifier. By default, asserts are turned on and it is recommended that users leave asserts on during development.</p>
<p><b> Building the driver </b></p>
<p>The HDMI TX driver is composed of several source files. This allows the user to build and link only those parts of the driver that are necessary.</p>
<pre>
 MODIFICATION HISTORY:
s
 Ver   Who    Date     Changes
</p>
<hr/>
<p>
 1.00  EB     22/05/18 Initial release.
 </pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx1___scdc_field.html">XV_HdmiTx1_ScdcField</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains DDC registers offset, mask, shift.  <a href="struct_x_v___hdmi_tx1___scdc_field.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx1___config.html">XV_HdmiTx1_Config</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains configuration information for the HDMI TX core.  <a href="struct_x_v___hdmi_tx1___config.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx1___audio_stream.html">XV_HdmiTx1_AudioStream</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains audio stream specific data structure.  <a href="struct_x_v___hdmi_tx1___audio_stream.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx1___stream.html">XV_HdmiTx1_Stream</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">This typedef contains HDMI TX stream specific data structure.  <a href="struct_x_v___hdmi_tx1___stream.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">The <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> driver instance data.  <a href="struct_x_v___hdmi_tx1.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a6926aebb0befff7242eceee32a5f74cb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a6926aebb0befff7242eceee32a5f74cb">XV_HDMITX1_H_</a></td></tr>
<tr class="memdesc:a6926aebb0befff7242eceee32a5f74cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#a6926aebb0befff7242eceee32a5f74cb">More...</a><br/></td></tr>
<tr class="separator:a6926aebb0befff7242eceee32a5f74cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
Enumerations</h2></td></tr>
<tr><td colspan="2"><div class="groupHeader">Handler Types</div></td></tr>
<tr class="memitem:af9b30d0cba10a37e4719114fe400ea64"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#af9b30d0cba10a37e4719114fe400ea64">XV_HdmiTx1_HandlerType</a> </td></tr>
<tr class="memdesc:af9b30d0cba10a37e4719114fe400ea64"><td class="mdescLeft">&#160;</td><td class="mdescRight">These constants specify different types of handler and used to differentiate interrupt requests from peripheral.  <a href="xv__hdmitx1_8h.html#af9b30d0cba10a37e4719114fe400ea64">More...</a><br/></td></tr>
<tr class="separator:af9b30d0cba10a37e4719114fe400ea64"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">HDMI TX stream status</div></td></tr>
<tr class="memitem:afdfa1de50e03ac7983bc1dff7d4d0a4f"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiTx1_State</b> </td></tr>
<tr class="separator:afdfa1de50e03ac7983bc1dff7d4d0a4f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">HDMI TX audio format</div></td></tr>
<tr class="memitem:afd608daa8882c5fa37f9b47e732415ab"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiTx1_AudioFormatType</b> </td></tr>
<tr class="separator:afd608daa8882c5fa37f9b47e732415ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">HDMI TX SCDC Fields</div></td></tr>
<tr class="memitem:a89af94c46325012d2281a258ec1bd03b"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiTx1_ScdcFieldType</b> </td></tr>
<tr class="separator:a89af94c46325012d2281a258ec1bd03b"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
HDMI TX CTS and N Source</h2></td></tr>
<tr class="memitem:ab4c65e1485f6003c182e86c2423d1934"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ab4c65e1485f6003c182e86c2423d1934">XV_HdmiTx1_GetTime1Ms</a>(InstancePtr)&#160;&#160;&#160;(InstancePtr)-&gt;Config.AxiLiteClkFreq/1000</td></tr>
<tr class="memdesc:ab4c65e1485f6003c182e86c2423d1934"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro returns the clock cycles required to count up to 1MS with respect to AXI Lite Frequency.  <a href="#ab4c65e1485f6003c182e86c2423d1934">More...</a><br/></td></tr>
<tr class="separator:ab4c65e1485f6003c182e86c2423d1934"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a18585e7fc532ca0145dd173b60425d6c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a18585e7fc532ca0145dd173b60425d6c">XV_HdmiTx1_GetTime10Ms</a>(InstancePtr)&#160;&#160;&#160;(InstancePtr)-&gt;Config.AxiLiteClkFreq/100</td></tr>
<tr class="memdesc:a18585e7fc532ca0145dd173b60425d6c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro returns the clock cycles required to count up to 10MS with respect to AXI Lite Frequency.  <a href="#a18585e7fc532ca0145dd173b60425d6c">More...</a><br/></td></tr>
<tr class="separator:a18585e7fc532ca0145dd173b60425d6c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a71d09e8eb72fc3354a2ae431cdd05577"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a71d09e8eb72fc3354a2ae431cdd05577">XV_HdmiTx1_GetVersion</a>(InstancePtr)</td></tr>
<tr class="memdesc:a71d09e8eb72fc3354a2ae431cdd05577"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the TX version.  <a href="#a71d09e8eb72fc3354a2ae431cdd05577">More...</a><br/></td></tr>
<tr class="separator:a71d09e8eb72fc3354a2ae431cdd05577"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a472ba57070bc4e736991f19f06490680"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a472ba57070bc4e736991f19f06490680">XV_HdmiTx1_Reset</a>(InstancePtr, Reset)</td></tr>
<tr class="memdesc:a472ba57070bc4e736991f19f06490680"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro asserts or releases the HDMI TX reset.  <a href="#a472ba57070bc4e736991f19f06490680">More...</a><br/></td></tr>
<tr class="separator:a472ba57070bc4e736991f19f06490680"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a669f967b9baf869d60aa8dc35297ee3a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a669f967b9baf869d60aa8dc35297ee3a">XV_HdmiTx1_SetScrambler</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:a669f967b9baf869d60aa8dc35297ee3a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro controls the HDMI TX Scrambler.  <a href="#a669f967b9baf869d60aa8dc35297ee3a">More...</a><br/></td></tr>
<tr class="separator:a669f967b9baf869d60aa8dc35297ee3a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7af7805735f505cdea41cfbbf8bea17b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a7af7805735f505cdea41cfbbf8bea17b">XV_HdmiTx1_Bridge_yuv420</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:a7af7805735f505cdea41cfbbf8bea17b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro controls the YUV420 mode for video bridge.  <a href="#a7af7805735f505cdea41cfbbf8bea17b">More...</a><br/></td></tr>
<tr class="separator:a7af7805735f505cdea41cfbbf8bea17b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a112885de6b7be79d903f1c8abee64161"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a112885de6b7be79d903f1c8abee64161">XV_HdmiTx1_Bridge_pixel</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:a112885de6b7be79d903f1c8abee64161"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro controls the Pixel Repeat mode for video bridge.  <a href="#a112885de6b7be79d903f1c8abee64161">More...</a><br/></td></tr>
<tr class="separator:a112885de6b7be79d903f1c8abee64161"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aee2b7ea5870d1eb94eb90bbfe2130e50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#aee2b7ea5870d1eb94eb90bbfe2130e50">XV_HdmiTx1_PioEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:aee2b7ea5870d1eb94eb90bbfe2130e50"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the HDMI TX PIO peripheral.  <a href="#aee2b7ea5870d1eb94eb90bbfe2130e50">More...</a><br/></td></tr>
<tr class="separator:aee2b7ea5870d1eb94eb90bbfe2130e50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adc65c495c5346d5026795fd9ae6d7cd7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#adc65c495c5346d5026795fd9ae6d7cd7">XV_HdmiTx1_PioDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:adc65c495c5346d5026795fd9ae6d7cd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the HDMI TX PIO peripheral.  <a href="#adc65c495c5346d5026795fd9ae6d7cd7">More...</a><br/></td></tr>
<tr class="separator:adc65c495c5346d5026795fd9ae6d7cd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac1422deaecdcaa680769832bbcfaf8a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ac1422deaecdcaa680769832bbcfaf8a7">XV_HdmiTx1_PioIntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ac1422deaecdcaa680769832bbcfaf8a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables interrupt in the HDMI TX PIO peripheral.  <a href="#ac1422deaecdcaa680769832bbcfaf8a7">More...</a><br/></td></tr>
<tr class="separator:ac1422deaecdcaa680769832bbcfaf8a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8acc56c70efc79834e9411b6cff105c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a8acc56c70efc79834e9411b6cff105c5">XV_HdmiTx1_PioIntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a8acc56c70efc79834e9411b6cff105c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables interrupt in the HDMI TX PIO peripheral.  <a href="#a8acc56c70efc79834e9411b6cff105c5">More...</a><br/></td></tr>
<tr class="separator:a8acc56c70efc79834e9411b6cff105c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7e5757f2158d4aae374aa076fbc147e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a7e5757f2158d4aae374aa076fbc147e7">XV_HdmiTx1_PioIntrClear</a>(InstancePtr)</td></tr>
<tr class="memdesc:a7e5757f2158d4aae374aa076fbc147e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro clears HDMI TX PIO interrupt.  <a href="#a7e5757f2158d4aae374aa076fbc147e7">More...</a><br/></td></tr>
<tr class="separator:a7e5757f2158d4aae374aa076fbc147e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa2bd58dc021ee4fe7b52eca1125f39b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#aa2bd58dc021ee4fe7b52eca1125f39b6">XV_HdmiTx1_DdcEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:aa2bd58dc021ee4fe7b52eca1125f39b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the HDMI TX Display Data Channel (DDC) peripheral.  <a href="#aa2bd58dc021ee4fe7b52eca1125f39b6">More...</a><br/></td></tr>
<tr class="separator:aa2bd58dc021ee4fe7b52eca1125f39b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a48c24836f4ff579b8bf3ed1dfc298747"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a48c24836f4ff579b8bf3ed1dfc298747">XV_HdmiTx1_DdcDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a48c24836f4ff579b8bf3ed1dfc298747"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the HDMI TX Display Data Channel (DDC) peripheral.  <a href="#a48c24836f4ff579b8bf3ed1dfc298747">More...</a><br/></td></tr>
<tr class="separator:a48c24836f4ff579b8bf3ed1dfc298747"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8e3011104d6800a0bf73887c3ad5cad5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a8e3011104d6800a0bf73887c3ad5cad5">XV_HdmiTx1_DdcIntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a8e3011104d6800a0bf73887c3ad5cad5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables interrupt in the HDMI TX DDC peripheral.  <a href="#a8e3011104d6800a0bf73887c3ad5cad5">More...</a><br/></td></tr>
<tr class="separator:a8e3011104d6800a0bf73887c3ad5cad5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0a0262addeb5640e4b2d681202559056"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a0a0262addeb5640e4b2d681202559056">XV_HdmiTx1_DdcIntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a0a0262addeb5640e4b2d681202559056"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables interrupt in the HDMI TX DDC peripheral.  <a href="#a0a0262addeb5640e4b2d681202559056">More...</a><br/></td></tr>
<tr class="separator:a0a0262addeb5640e4b2d681202559056"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a4bb321f73f08e71204821bb3c68b3d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a1a4bb321f73f08e71204821bb3c68b3d">XV_HdmiTx1_DdcIntrClear</a>(InstancePtr)</td></tr>
<tr class="memdesc:a1a4bb321f73f08e71204821bb3c68b3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro clears HDMI TX DDC interrupt.  <a href="#a1a4bb321f73f08e71204821bb3c68b3d">More...</a><br/></td></tr>
<tr class="separator:a1a4bb321f73f08e71204821bb3c68b3d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a885cea7ad25eb7470e839cbe329b8ec4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a885cea7ad25eb7470e839cbe329b8ec4">XV_HdmiTx1_AuxDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a885cea7ad25eb7470e839cbe329b8ec4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the HDMI TX Auxiliary (AUX) peripheral.  <a href="#a885cea7ad25eb7470e839cbe329b8ec4">More...</a><br/></td></tr>
<tr class="separator:a885cea7ad25eb7470e839cbe329b8ec4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeefc5a50cd7f61f65466eec26592b3c4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#aeefc5a50cd7f61f65466eec26592b3c4">XV_HdmiTx1_AuxIntrEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:aeefc5a50cd7f61f65466eec26592b3c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables interrupt in the HDMI TX AUX peripheral.  <a href="#aeefc5a50cd7f61f65466eec26592b3c4">More...</a><br/></td></tr>
<tr class="separator:aeefc5a50cd7f61f65466eec26592b3c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae2f8cf0015a6f22105b8e63f0388ff28"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ae2f8cf0015a6f22105b8e63f0388ff28">XV_HdmiTx1_VrrControl</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:ae2f8cf0015a6f22105b8e63f0388ff28"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro allows enabling/disabling of VRR in HDMI Tx.  <a href="#ae2f8cf0015a6f22105b8e63f0388ff28">More...</a><br/></td></tr>
<tr class="separator:ae2f8cf0015a6f22105b8e63f0388ff28"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a30ec57f9a1a00ca63e9d3fdecf5204"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a1a30ec57f9a1a00ca63e9d3fdecf5204">XV_HdmiTx1_FSyncControl</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:a1a30ec57f9a1a00ca63e9d3fdecf5204"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro allows enabling/disabling of FSync in HDMI Tx.  <a href="#a1a30ec57f9a1a00ca63e9d3fdecf5204">More...</a><br/></td></tr>
<tr class="separator:a1a30ec57f9a1a00ca63e9d3fdecf5204"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae2165f794a177f55510c8352ecc9a98b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ae2165f794a177f55510c8352ecc9a98b">XV_HdmiTx1_DynHdr_DM_Enable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ae2165f794a177f55510c8352ecc9a98b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables the data mover for Dynamic HDR in HDMI Tx.  <a href="#ae2165f794a177f55510c8352ecc9a98b">More...</a><br/></td></tr>
<tr class="separator:ae2165f794a177f55510c8352ecc9a98b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a18b2a682a5a6928c3cdee2456563227c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a18b2a682a5a6928c3cdee2456563227c">XV_HdmiTx1_DynHdr_DM_Disable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a18b2a682a5a6928c3cdee2456563227c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables the data mover for Dynamic HDR in HDMI Tx.  <a href="#a18b2a682a5a6928c3cdee2456563227c">More...</a><br/></td></tr>
<tr class="separator:a18b2a682a5a6928c3cdee2456563227c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a725ca58c53140f1988f01a8905b988e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a725ca58c53140f1988f01a8905b988e9">XV_HdmiTx1_DynHdr_Control</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:a725ca58c53140f1988f01a8905b988e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro allows enabling/disabling of Dynamic HDR in HDMI Tx.  <a href="#a725ca58c53140f1988f01a8905b988e9">More...</a><br/></td></tr>
<tr class="separator:a725ca58c53140f1988f01a8905b988e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b19bc8021786cf6f894465049fe5388"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a2b19bc8021786cf6f894465049fe5388">XV_HdmiTx1_DynHdr_FAPA_Control</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:a2b19bc8021786cf6f894465049fe5388"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro allows enabling/disabling of FAPA Location Dynamic HDR in HDMI Tx.  <a href="#a2b19bc8021786cf6f894465049fe5388">More...</a><br/></td></tr>
<tr class="separator:a2b19bc8021786cf6f894465049fe5388"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad1d2c212b436c956d75a234da2eaaf81"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ad1d2c212b436c956d75a234da2eaaf81">XV_HdmiTx1_DynHdr_GOF_Control</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:ad1d2c212b436c956d75a234da2eaaf81"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro allows enabling/disabling of GOF Dynamic HDR in HDMI Tx.  <a href="#ad1d2c212b436c956d75a234da2eaaf81">More...</a><br/></td></tr>
<tr class="separator:ad1d2c212b436c956d75a234da2eaaf81"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ade55c5cc63a3f03ea6d31044ae6ac6dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ade55c5cc63a3f03ea6d31044ae6ac6dc">XV_HdmiTx1_DynHdr_GOFVal_Control</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:ade55c5cc63a3f03ea6d31044ae6ac6dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro allows set/clear of GOF Value Dynamic HDR in HDMI Tx.  <a href="#ade55c5cc63a3f03ea6d31044ae6ac6dc">More...</a><br/></td></tr>
<tr class="separator:ade55c5cc63a3f03ea6d31044ae6ac6dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8e5aac8b73e29cead73018767a441003"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a8e5aac8b73e29cead73018767a441003">XV_HdmiTx1_DynHdr_MTW_Clear</a>(InstancePtr)</td></tr>
<tr class="memdesc:a8e5aac8b73e29cead73018767a441003"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro allows to set the MTW bit to clear it for Dynamic HDR in HDMI Tx.  <a href="#a8e5aac8b73e29cead73018767a441003">More...</a><br/></td></tr>
<tr class="separator:a8e5aac8b73e29cead73018767a441003"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adfe9f81467882df525e80e6e0da2eeb4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#adfe9f81467882df525e80e6e0da2eeb4">XV_HdmiTx1_DynHdr_GetReadStatus</a>(InstancePtr)</td></tr>
<tr class="memdesc:adfe9f81467882df525e80e6e0da2eeb4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro gets the read status of Data Mover for Dynamic HDR in HDMI Tx.  <a href="#adfe9f81467882df525e80e6e0da2eeb4">More...</a><br/></td></tr>
<tr class="separator:adfe9f81467882df525e80e6e0da2eeb4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae7239649dafa25907a4f4b8101248395"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ae7239649dafa25907a4f4b8101248395">XV_HdmiTx1_DynHdr_SetPacket</a>(InstancePtr, PktLen, PktType)</td></tr>
<tr class="memdesc:ae7239649dafa25907a4f4b8101248395"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sets the Header packet type and length for Dynamic HDR in HDMI Tx.  <a href="#ae7239649dafa25907a4f4b8101248395">More...</a><br/></td></tr>
<tr class="separator:ae7239649dafa25907a4f4b8101248395"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5ef7d028f59c8bbeb435526b2bdb7ee6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a5ef7d028f59c8bbeb435526b2bdb7ee6">XV_HdmiTx1_DynHdr_SetAddr</a>(InstancePtr, Addr)</td></tr>
<tr class="memdesc:a5ef7d028f59c8bbeb435526b2bdb7ee6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sets the buffer address for Dynamic HDR in HDMI Tx.  <a href="#a5ef7d028f59c8bbeb435526b2bdb7ee6">More...</a><br/></td></tr>
<tr class="separator:a5ef7d028f59c8bbeb435526b2bdb7ee6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0c8aaaa8fc3e83d9bbfb3cfd4c32cae0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a0c8aaaa8fc3e83d9bbfb3cfd4c32cae0">XV_HdmiTx1_AuxIntrDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a0c8aaaa8fc3e83d9bbfb3cfd4c32cae0"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables interrupt in the HDMI TX AUX peripheral.  <a href="#a0c8aaaa8fc3e83d9bbfb3cfd4c32cae0">More...</a><br/></td></tr>
<tr class="separator:a0c8aaaa8fc3e83d9bbfb3cfd4c32cae0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac80822fe192ddd125e321cdf4c9d4608"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ac80822fe192ddd125e321cdf4c9d4608">XV_HdmiTx1_AudioDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ac80822fe192ddd125e321cdf4c9d4608"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables audio in HDMI TX core.  <a href="#ac80822fe192ddd125e321cdf4c9d4608">More...</a><br/></td></tr>
<tr class="separator:ac80822fe192ddd125e321cdf4c9d4608"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af3a6c361d3eb8f9bc43cc1d4f6bc2269"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#af3a6c361d3eb8f9bc43cc1d4f6bc2269">XV_HdmiTx1_SetMode</a>(InstancePtr)</td></tr>
<tr class="memdesc:af3a6c361d3eb8f9bc43cc1d4f6bc2269"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sets the mode bit.  <a href="#af3a6c361d3eb8f9bc43cc1d4f6bc2269">More...</a><br/></td></tr>
<tr class="separator:af3a6c361d3eb8f9bc43cc1d4f6bc2269"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4ed1526a4760bbcb4b978ff021fbc360"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a4ed1526a4760bbcb4b978ff021fbc360">XV_HdmiTx1_ClearMode</a>(InstancePtr)</td></tr>
<tr class="memdesc:a4ed1526a4760bbcb4b978ff021fbc360"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro clears the mode bit.  <a href="#a4ed1526a4760bbcb4b978ff021fbc360">More...</a><br/></td></tr>
<tr class="separator:a4ed1526a4760bbcb4b978ff021fbc360"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a105919aa6ac08f5ca806441ca1199b36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a105919aa6ac08f5ca806441ca1199b36">XV_HdmiTx1_GetMode</a>(InstancePtr)</td></tr>
<tr class="memdesc:a105919aa6ac08f5ca806441ca1199b36"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro provides the current mode.  <a href="#a105919aa6ac08f5ca806441ca1199b36">More...</a><br/></td></tr>
<tr class="separator:a105919aa6ac08f5ca806441ca1199b36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a426ea58febc9ac3fdd48e9a9210ea395"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a426ea58febc9ac3fdd48e9a9210ea395">XV_HdmiTx1_GetSampleRate</a>(InstancePtr)&#160;&#160;&#160;(InstancePtr)-&gt;Stream.SampleRate</td></tr>
<tr class="memdesc:a426ea58febc9ac3fdd48e9a9210ea395"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro provides the current sample rate.  <a href="#a426ea58febc9ac3fdd48e9a9210ea395">More...</a><br/></td></tr>
<tr class="separator:a426ea58febc9ac3fdd48e9a9210ea395"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a48b12eca7ac57575d26fd4275922c209"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a48b12eca7ac57575d26fd4275922c209">XV_HdmiTx1_GetAudioChannels</a>(InstancePtr)&#160;&#160;&#160;(InstancePtr)-&gt;Stream.Audio.Channels</td></tr>
<tr class="memdesc:a48b12eca7ac57575d26fd4275922c209"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro provides the active audio channels.  <a href="#a48b12eca7ac57575d26fd4275922c209">More...</a><br/></td></tr>
<tr class="separator:a48b12eca7ac57575d26fd4275922c209"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae9890b243a18bdef91ea4301400fe164"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ae9890b243a18bdef91ea4301400fe164">XV_HdmiTx1_GetPixelPackingPhase</a>(InstancePtr)</td></tr>
<tr class="memdesc:ae9890b243a18bdef91ea4301400fe164"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro provides the current pixel packing phase.  <a href="#ae9890b243a18bdef91ea4301400fe164">More...</a><br/></td></tr>
<tr class="separator:ae9890b243a18bdef91ea4301400fe164"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2100b1d5fae612b83ca0ccfbca59d9ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a2100b1d5fae612b83ca0ccfbca59d9ce">XV_HdmiTx1_MaskDisable</a>(InstancePtr)</td></tr>
<tr class="memdesc:a2100b1d5fae612b83ca0ccfbca59d9ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro disables video mask in HDMI TX core.  <a href="#a2100b1d5fae612b83ca0ccfbca59d9ce">More...</a><br/></td></tr>
<tr class="separator:a2100b1d5fae612b83ca0ccfbca59d9ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac82eb2360dcea3ef22415e7c22832d2a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ac82eb2360dcea3ef22415e7c22832d2a">XV_HdmiTx1_MaskEnable</a>(InstancePtr)</td></tr>
<tr class="memdesc:ac82eb2360dcea3ef22415e7c22832d2a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables video mask in HDMI TX core.  <a href="#ac82eb2360dcea3ef22415e7c22832d2a">More...</a><br/></td></tr>
<tr class="separator:ac82eb2360dcea3ef22415e7c22832d2a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5c88bd8ccdac3d52e52f7d2424a6c87a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a5c88bd8ccdac3d52e52f7d2424a6c87a">XV_HdmiTx1_MaskNoise</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:a5c88bd8ccdac3d52e52f7d2424a6c87a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables or disables the noise in the video mask.  <a href="#a5c88bd8ccdac3d52e52f7d2424a6c87a">More...</a><br/></td></tr>
<tr class="separator:a5c88bd8ccdac3d52e52f7d2424a6c87a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1fb069b9cad8d5bb6eb00e951ec8ca0d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a1fb069b9cad8d5bb6eb00e951ec8ca0d">XV_HdmiTx1_MaskSetRed</a>(InstancePtr, Value)</td></tr>
<tr class="memdesc:a1fb069b9cad8d5bb6eb00e951ec8ca0d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sets the red component value in the video mask.  <a href="#a1fb069b9cad8d5bb6eb00e951ec8ca0d">More...</a><br/></td></tr>
<tr class="separator:a1fb069b9cad8d5bb6eb00e951ec8ca0d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab1f3f7aa051a3fb35c1af544a57152ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ab1f3f7aa051a3fb35c1af544a57152ae">XV_HdmiTx1_MaskSetGreen</a>(InstancePtr, Value)</td></tr>
<tr class="memdesc:ab1f3f7aa051a3fb35c1af544a57152ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sets the green component value in the video mask.  <a href="#ab1f3f7aa051a3fb35c1af544a57152ae">More...</a><br/></td></tr>
<tr class="separator:ab1f3f7aa051a3fb35c1af544a57152ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac855dfb7ad3b16fbae667da7c09ea20b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ac855dfb7ad3b16fbae667da7c09ea20b">XV_HdmiTx1_MaskSetBlue</a>(InstancePtr, Value)</td></tr>
<tr class="memdesc:ac855dfb7ad3b16fbae667da7c09ea20b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro sets the blue component value in the video mask.  <a href="#ac855dfb7ad3b16fbae667da7c09ea20b">More...</a><br/></td></tr>
<tr class="separator:ac855dfb7ad3b16fbae667da7c09ea20b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a58c3a99be0feecd24bd3835e356656a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a58c3a99be0feecd24bd3835e356656a2">XV_HdmiTx1_IsMasked</a>(InstancePtr)</td></tr>
<tr class="memdesc:a58c3a99be0feecd24bd3835e356656a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro provides the current video mask mode.  <a href="#a58c3a99be0feecd24bd3835e356656a2">More...</a><br/></td></tr>
<tr class="separator:a58c3a99be0feecd24bd3835e356656a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9654f55c13fef03588ff7d4c870fc37a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a9654f55c13fef03588ff7d4c870fc37a">XV_HdmiTx1_DscControl</a>(InstancePtr, SetClr)</td></tr>
<tr class="memdesc:a9654f55c13fef03588ff7d4c870fc37a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro allows enabling/disabling of DSC in HDMI-TX.  <a href="#a9654f55c13fef03588ff7d4c870fc37a">More...</a><br/></td></tr>
<tr class="separator:a9654f55c13fef03588ff7d4c870fc37a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3feb2d8f651db69c07d0a28f2f367ab9"><td class="memItemLeft" align="right" valign="top">enum &#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiTx1_CTSNSource</b> </td></tr>
<tr class="separator:a3feb2d8f651db69c07d0a28f2f367ab9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5bb0fa4a27e544cf4df3fa3aad14011a"><td class="memItemLeft" align="right" valign="top">typedef void(*&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a5bb0fa4a27e544cf4df3fa3aad14011a">XV_HdmiTx1_Callback</a> )(void *CallbackRef)</td></tr>
<tr class="memdesc:a5bb0fa4a27e544cf4df3fa3aad14011a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Callback type for Vsync event interrupt.  <a href="#a5bb0fa4a27e544cf4df3fa3aad14011a">More...</a><br/></td></tr>
<tr class="separator:a5bb0fa4a27e544cf4df3fa3aad14011a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a91a4f806f19c4269cafee965b92359c1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_x_v___hdmi_tx1___config.html">XV_HdmiTx1_Config</a> *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a91a4f806f19c4269cafee965b92359c1">XV_HdmiTx1_LookupConfig</a> (u16 DeviceId)</td></tr>
<tr class="memdesc:a91a4f806f19c4269cafee965b92359c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns a reference to an <a class="el" href="struct_x_v___hdmi_tx1___config.html" title="This typedef contains configuration information for the HDMI TX core. ">XV_HdmiTx1_Config</a> structure based on the core id, <em>DeviceId</em>.  <a href="#a91a4f806f19c4269cafee965b92359c1">More...</a><br/></td></tr>
<tr class="separator:a91a4f806f19c4269cafee965b92359c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ade49d67af0d4ac0c3d5756a5cfdfe15f"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, <a class="el" href="struct_x_v___hdmi_tx1___config.html">XV_HdmiTx1_Config</a> *CfgPtr, UINTPTR EffectiveAddr)</td></tr>
<tr class="memdesc:ade49d67af0d4ac0c3d5756a5cfdfe15f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initializes the HDMI TX core.  <a href="#ade49d67af0d4ac0c3d5756a5cfdfe15f">More...</a><br/></td></tr>
<tr class="separator:ade49d67af0d4ac0c3d5756a5cfdfe15f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa350caac92add60e1c85f257dbf88bdd"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#aa350caac92add60e1c85f257dbf88bdd">XV_HdmiTx1_SetHdmiFrlMode</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:aa350caac92add60e1c85f257dbf88bdd"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the core into HDMI FRL mode.  <a href="#aa350caac92add60e1c85f257dbf88bdd">More...</a><br/></td></tr>
<tr class="separator:aa350caac92add60e1c85f257dbf88bdd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a214597c0aaa431427bb76ec6948563b8"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a214597c0aaa431427bb76ec6948563b8">XV_HdmiTx1_SetHdmiTmdsMode</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a214597c0aaa431427bb76ec6948563b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the core into HDMI TMDS mode.  <a href="#a214597c0aaa431427bb76ec6948563b8">More...</a><br/></td></tr>
<tr class="separator:a214597c0aaa431427bb76ec6948563b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abaf1a4638cb906d3ead0e42630727ad1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#abaf1a4638cb906d3ead0e42630727ad1">XV_HdmiTx1_SetDviMode</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:abaf1a4638cb906d3ead0e42630727ad1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the core into DVI mode.  <a href="#abaf1a4638cb906d3ead0e42630727ad1">More...</a><br/></td></tr>
<tr class="separator:abaf1a4638cb906d3ead0e42630727ad1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1b7d74b3288271064644bda7857a1c8b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a1b7d74b3288271064644bda7857a1c8b">XV_HdmiTx1_AuxEnable</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a1b7d74b3288271064644bda7857a1c8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function enables the HDMI TX Auxiliary (AUX) peripheral.  <a href="#a1b7d74b3288271064644bda7857a1c8b">More...</a><br/></td></tr>
<tr class="separator:a1b7d74b3288271064644bda7857a1c8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae842f2e11b05dbc07382f202bffbf7ea"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ae842f2e11b05dbc07382f202bffbf7ea">XV_HdmiTx1_AudioEnable</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ae842f2e11b05dbc07382f202bffbf7ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro enables audio in HDMI TX core.  <a href="#ae842f2e11b05dbc07382f202bffbf7ea">More...</a><br/></td></tr>
<tr class="separator:ae842f2e11b05dbc07382f202bffbf7ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a626c53ccaef2fea0d712d363e80691ac"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a626c53ccaef2fea0d712d363e80691ac">XV_HdmiTx1_Clear</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a626c53ccaef2fea0d712d363e80691ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clear the HDMI TX variables and sets it to the defaults.  <a href="#a626c53ccaef2fea0d712d363e80691ac">More...</a><br/></td></tr>
<tr class="separator:a626c53ccaef2fea0d712d363e80691ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abc7b6f6ccf8cebbdbd102c9ce612cd96"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#abc7b6f6ccf8cebbdbd102c9ce612cd96">XV_HdmiTx1_LookupVic</a> (XVidC_VideoMode VideoMode)</td></tr>
<tr class="memdesc:abc7b6f6ccf8cebbdbd102c9ce612cd96"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides video identification code of video mode.  <a href="#abc7b6f6ccf8cebbdbd102c9ce612cd96">More...</a><br/></td></tr>
<tr class="separator:abc7b6f6ccf8cebbdbd102c9ce612cd96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aba2f50da08ab46699dcee07db1d106c1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aba2f50da08ab46699dcee07db1d106c1"></a>
XVidC_VideoMode&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiTx1_GetVideoModeFromVic</b> (u8 Vic)</td></tr>
<tr class="separator:aba2f50da08ab46699dcee07db1d106c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7a20221c997a381a61b4e7e98c5a4370"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a7a20221c997a381a61b4e7e98c5a4370">XV_HdmiTx1_SetStream</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, XVidC_VideoTiming VideoTiming, XVidC_FrameRate FrameRate, XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, XVidC_PixelsPerClock Ppc, XVidC_3DInfo *Info3D, u8 FVaFactor, u8 VrrEnabled, u8 CnmvrrEnabled, u64 *TmdsClk)</td></tr>
<tr class="memdesc:a7a20221c997a381a61b4e7e98c5a4370"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the HDMI TX stream parameters.  <a href="#a7a20221c997a381a61b4e7e98c5a4370">More...</a><br/></td></tr>
<tr class="separator:a7a20221c997a381a61b4e7e98c5a4370"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2fdc16b8be464514b4d72ddfb947cee9"><td class="memItemLeft" align="right" valign="top">u64&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a2fdc16b8be464514b4d72ddfb947cee9">XV_HdmiTx1_GetTmdsClk</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a2fdc16b8be464514b4d72ddfb947cee9"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets and return the TMDS Clock based on Video Parameter from the InstancePtr.  <a href="#a2fdc16b8be464514b4d72ddfb947cee9">More...</a><br/></td></tr>
<tr class="separator:a2fdc16b8be464514b4d72ddfb947cee9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adf9e5c73a5f308d04eea85dd4db8f42f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#adf9e5c73a5f308d04eea85dd4db8f42f">XV_HdmiTx1_INT_VRST</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 Reset)</td></tr>
<tr class="memdesc:adf9e5c73a5f308d04eea85dd4db8f42f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function asserts or releases the HDMI TX Internal VRST.  <a href="#adf9e5c73a5f308d04eea85dd4db8f42f">More...</a><br/></td></tr>
<tr class="separator:adf9e5c73a5f308d04eea85dd4db8f42f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aecd47642f9aa91941d14c04543f73827"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#aecd47642f9aa91941d14c04543f73827">XV_HdmiTx1_INT_LRST</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 Reset)</td></tr>
<tr class="memdesc:aecd47642f9aa91941d14c04543f73827"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function asserts or releases the HDMI TX Internal LRST.  <a href="#aecd47642f9aa91941d14c04543f73827">More...</a><br/></td></tr>
<tr class="separator:aecd47642f9aa91941d14c04543f73827"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a73e17f2ac248affe52270168283ba45f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a73e17f2ac248affe52270168283ba45f">XV_HdmiTx1_EXT_VRST</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 Reset)</td></tr>
<tr class="memdesc:a73e17f2ac248affe52270168283ba45f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function asserts or releases the HDMI TX External VRST.  <a href="#a73e17f2ac248affe52270168283ba45f">More...</a><br/></td></tr>
<tr class="separator:a73e17f2ac248affe52270168283ba45f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a74e6c88c1599a6f0290c5db420bc8d50"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a74e6c88c1599a6f0290c5db420bc8d50">XV_HdmiTx1_EXT_SYSRST</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 Reset)</td></tr>
<tr class="memdesc:a74e6c88c1599a6f0290c5db420bc8d50"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function asserts or releases the HDMI TX External SYSRST.  <a href="#a74e6c88c1599a6f0290c5db420bc8d50">More...</a><br/></td></tr>
<tr class="separator:a74e6c88c1599a6f0290c5db420bc8d50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab1fbe68d90e50414180d190c9f4c5a75"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ab1fbe68d90e50414180d190c9f4c5a75">XV_HdmiTx1_SetGcpAvmuteBit</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ab1fbe68d90e50414180d190c9f4c5a75"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the HDMI TX AUX GCP register AVMUTE bit.  <a href="#ab1fbe68d90e50414180d190c9f4c5a75">More...</a><br/></td></tr>
<tr class="separator:ab1fbe68d90e50414180d190c9f4c5a75"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afad06f0251d19842573b1f2695149e8c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#afad06f0251d19842573b1f2695149e8c">XV_HdmiTx1_ClearGcpAvmuteBit</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:afad06f0251d19842573b1f2695149e8c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears the HDMI TX AUX GCP register AVMUTE bit.  <a href="#afad06f0251d19842573b1f2695149e8c">More...</a><br/></td></tr>
<tr class="separator:afad06f0251d19842573b1f2695149e8c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8052b352068e63f196e7cb4eaba721e1"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a8052b352068e63f196e7cb4eaba721e1">XV_HdmiTx1_SetGcpClearAvmuteBit</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a8052b352068e63f196e7cb4eaba721e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the HDMI TX AUX GCP register CLEAR_AVMUTE bit.  <a href="#a8052b352068e63f196e7cb4eaba721e1">More...</a><br/></td></tr>
<tr class="separator:a8052b352068e63f196e7cb4eaba721e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae56341f568a34cc9c677f5d8c822e156"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ae56341f568a34cc9c677f5d8c822e156">XV_HdmiTx1_ClearGcpClearAvmuteBit</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ae56341f568a34cc9c677f5d8c822e156"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears the HDMI TX AUX GCP register CLEAR_AVMUTE bit.  <a href="#ae56341f568a34cc9c677f5d8c822e156">More...</a><br/></td></tr>
<tr class="separator:ae56341f568a34cc9c677f5d8c822e156"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a606cf8a2a1153de19c66925b9d462636"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a606cf8a2a1153de19c66925b9d462636">XV_HdmiTx1_SetPixelRate</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a606cf8a2a1153de19c66925b9d462636"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the pixel rate at output.  <a href="#a606cf8a2a1153de19c66925b9d462636">More...</a><br/></td></tr>
<tr class="separator:a606cf8a2a1153de19c66925b9d462636"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab1c2a996dc8766605df5df4d6a37eb45"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ab1c2a996dc8766605df5df4d6a37eb45">XV_HdmiTx1_SetSampleRate</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 SampleRate)</td></tr>
<tr class="memdesc:ab1c2a996dc8766605df5df4d6a37eb45"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the sample rate at output.  <a href="#ab1c2a996dc8766605df5df4d6a37eb45">More...</a><br/></td></tr>
<tr class="separator:ab1c2a996dc8766605df5df4d6a37eb45"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0aa5bbd57a95785df766d6d5a919479a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a0aa5bbd57a95785df766d6d5a919479a">XV_HdmiTx1_SetColorFormat</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a0aa5bbd57a95785df766d6d5a919479a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the color format.  <a href="#a0aa5bbd57a95785df766d6d5a919479a">More...</a><br/></td></tr>
<tr class="separator:a0aa5bbd57a95785df766d6d5a919479a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a25379b09e782626e79fd3b785b671f2e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a25379b09e782626e79fd3b785b671f2e">XV_HdmiTx1_SetColorDepth</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a25379b09e782626e79fd3b785b671f2e"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the color depth.  <a href="#a25379b09e782626e79fd3b785b671f2e">More...</a><br/></td></tr>
<tr class="separator:a25379b09e782626e79fd3b785b671f2e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad3a48e290c617a6ede63a42f1d586364"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ad3a48e290c617a6ede63a42f1d586364">XV_HdmiTx1_IsStreamScrambled</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ad3a48e290c617a6ede63a42f1d586364"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides status of the stream.  <a href="#ad3a48e290c617a6ede63a42f1d586364">More...</a><br/></td></tr>
<tr class="separator:ad3a48e290c617a6ede63a42f1d586364"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa0ee62f31bc2ceaa6b7dd92618560a0a"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#aa0ee62f31bc2ceaa6b7dd92618560a0a">XV_HdmiTx1_IsStreamConnected</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:aa0ee62f31bc2ceaa6b7dd92618560a0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function provides the stream connected status.  <a href="#aa0ee62f31bc2ceaa6b7dd92618560a0a">More...</a><br/></td></tr>
<tr class="separator:aa0ee62f31bc2ceaa6b7dd92618560a0a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6c007b416e2eeb72cc040a16b285b57c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a6c007b416e2eeb72cc040a16b285b57c">XV_HdmiTx1_SetAxiClkFreq</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u32 ClkFreq)</td></tr>
<tr class="memdesc:a6c007b416e2eeb72cc040a16b285b57c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the AXI4-Lite Clock Frequency.  <a href="#a6c007b416e2eeb72cc040a16b285b57c">More...</a><br/></td></tr>
<tr class="separator:a6c007b416e2eeb72cc040a16b285b57c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0304469fda5cb9070c1c0db0c229f11c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a0304469fda5cb9070c1c0db0c229f11c">XV_HdmiTx1_DdcInit</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u32 Frequency)</td></tr>
<tr class="memdesc:a0304469fda5cb9070c1c0db0c229f11c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prepares TX DDC peripheral to use.  <a href="#a0304469fda5cb9070c1c0db0c229f11c">More...</a><br/></td></tr>
<tr class="separator:a0304469fda5cb9070c1c0db0c229f11c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab587002464f4dbfd8db9b39199bb4bdc"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 Slave, u16 Length, u8 *Buffer, u8 Stop)</td></tr>
<tr class="memdesc:ab587002464f4dbfd8db9b39199bb4bdc"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function writes data from DDC peripheral from given slave address.  <a href="#ab587002464f4dbfd8db9b39199bb4bdc">More...</a><br/></td></tr>
<tr class="separator:ab587002464f4dbfd8db9b39199bb4bdc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8e431bf1d16450b478448424d81e72ea"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 Slave, u16 Length, u8 *Buffer, u8 Stop)</td></tr>
<tr class="memdesc:a8e431bf1d16450b478448424d81e72ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads data from DDC peripheral from given slave address.  <a href="#a8e431bf1d16450b478448424d81e72ea">More...</a><br/></td></tr>
<tr class="separator:a8e431bf1d16450b478448424d81e72ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9a71a92b44c225aa265a3c5852971df7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a9a71a92b44c225aa265a3c5852971df7">XV_HdmiTx1_DdcReadReg</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 Slave, u16 Length, u8 RegAddr, u8 *Buffer)</td></tr>
<tr class="memdesc:a9a71a92b44c225aa265a3c5852971df7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads specified register from DDC peripheral from given slave address.  <a href="#a9a71a92b44c225aa265a3c5852971df7">More...</a><br/></td></tr>
<tr class="separator:a9a71a92b44c225aa265a3c5852971df7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab9b6a97a3396e177e52f69f6b5d88123"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ab9b6a97a3396e177e52f69f6b5d88123">XV_HdmiTx1_DdcWriteField</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, XV_HdmiTx1_ScdcFieldType Field, u8 Value)</td></tr>
<tr class="memdesc:ab9b6a97a3396e177e52f69f6b5d88123"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function writes the specified SCDC Field.  <a href="#ab9b6a97a3396e177e52f69f6b5d88123">More...</a><br/></td></tr>
<tr class="separator:ab9b6a97a3396e177e52f69f6b5d88123"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0ac2f0429e283d420ab2498273c288a4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a0ac2f0429e283d420ab2498273c288a4">XV_HdmiTx1_Aux_Dsc_Send_Header</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u32 Data)</td></tr>
<tr class="memdesc:a0ac2f0429e283d420ab2498273c288a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function transmits the DSC packet header.  <a href="#a0ac2f0429e283d420ab2498273c288a4">More...</a><br/></td></tr>
<tr class="separator:a0ac2f0429e283d420ab2498273c288a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afaf9e97accf4f26abbdac8ef9410dcab"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#afaf9e97accf4f26abbdac8ef9410dcab">XV_HdmiTx1_Aux_Dsc_Send_Data</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u32 Data)</td></tr>
<tr class="memdesc:afaf9e97accf4f26abbdac8ef9410dcab"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function transmits the DSC packet data.  <a href="#afaf9e97accf4f26abbdac8ef9410dcab">More...</a><br/></td></tr>
<tr class="separator:afaf9e97accf4f26abbdac8ef9410dcab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a49560390a20d63cec3fd7c79c2f44a76"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a49560390a20d63cec3fd7c79c2f44a76">XV_HdmiTx1_AuxSend</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a49560390a20d63cec3fd7c79c2f44a76"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function transmits the infoframes generated by the processor.  <a href="#a49560390a20d63cec3fd7c79c2f44a76">More...</a><br/></td></tr>
<tr class="separator:a49560390a20d63cec3fd7c79c2f44a76"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a83f6939b0f5205344a276489afe45223"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a83f6939b0f5205344a276489afe45223">XV_HdmiTx1_Scrambler</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a83f6939b0f5205344a276489afe45223"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function controls the scrambler.  <a href="#a83f6939b0f5205344a276489afe45223">More...</a><br/></td></tr>
<tr class="separator:a83f6939b0f5205344a276489afe45223"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af8b34671e3735035e8dd68f6bdbb7904"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#af8b34671e3735035e8dd68f6bdbb7904">XV_HdmiTx1_ClockRatio</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:af8b34671e3735035e8dd68f6bdbb7904"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function controls the TMDS clock ratio.  <a href="#af8b34671e3735035e8dd68f6bdbb7904">More...</a><br/></td></tr>
<tr class="separator:af8b34671e3735035e8dd68f6bdbb7904"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab2deec246bd2a50733347cdb293e7d59"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ab2deec246bd2a50733347cdb293e7d59">XV_HdmiTx1_DetectHdmi20</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ab2deec246bd2a50733347cdb293e7d59"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function detects connected sink is a HDMI 2.0/HDMI 1.4 sink device and sets appropriate flag in the TX stream.  <a href="#ab2deec246bd2a50733347cdb293e7d59">More...</a><br/></td></tr>
<tr class="separator:ab2deec246bd2a50733347cdb293e7d59"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a74ffa1683c6444f4ba05916b5c15312a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a74ffa1683c6444f4ba05916b5c15312a">XV_HdmiTx1_ShowSCDC</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a74ffa1683c6444f4ba05916b5c15312a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function shows the sinks SCDC registers.  <a href="#a74ffa1683c6444f4ba05916b5c15312a">More...</a><br/></td></tr>
<tr class="separator:a74ffa1683c6444f4ba05916b5c15312a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab0ff2a9927fe900b25456955341dfa31"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ab0ff2a9927fe900b25456955341dfa31">XV_HdmiTx1_Info</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ab0ff2a9927fe900b25456955341dfa31"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prints stream and timing information on STDIO/Uart console.  <a href="#ab0ff2a9927fe900b25456955341dfa31">More...</a><br/></td></tr>
<tr class="separator:ab0ff2a9927fe900b25456955341dfa31"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab79a6440a7ae1001abe1b5f6ab6e7c1b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ab79a6440a7ae1001abe1b5f6ab6e7c1b">XV_HdmiTx1_DebugInfo</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ab79a6440a7ae1001abe1b5f6ab6e7c1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prints debug information on STDIO/UART console.  <a href="#ab79a6440a7ae1001abe1b5f6ab6e7c1b">More...</a><br/></td></tr>
<tr class="separator:ab79a6440a7ae1001abe1b5f6ab6e7c1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7bd42ae44563fd0dc91d40c0dfe8d7c3"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a7bd42ae44563fd0dc91d40c0dfe8d7c3">XV_HdmiTx1_RegisterDebug</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a7bd42ae44563fd0dc91d40c0dfe8d7c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function prints out HDMI TX register.  <a href="#a7bd42ae44563fd0dc91d40c0dfe8d7c3">More...</a><br/></td></tr>
<tr class="separator:a7bd42ae44563fd0dc91d40c0dfe8d7c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae0d426d4100141b3e9f9d943197d07e8"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ae0d426d4100141b3e9f9d943197d07e8">XV_HdmiTx1_SetAudioChannels</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 Value)</td></tr>
<tr class="memdesc:ae0d426d4100141b3e9f9d943197d07e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the active audio channels.  <a href="#ae0d426d4100141b3e9f9d943197d07e8">More...</a><br/></td></tr>
<tr class="separator:ae0d426d4100141b3e9f9d943197d07e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a23a20e6c1144064686e03fd0650ec46f"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a23a20e6c1144064686e03fd0650ec46f">XV_HdmiTx1_SetAudioFormat</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, XV_HdmiTx1_AudioFormatType Value)</td></tr>
<tr class="memdesc:a23a20e6c1144064686e03fd0650ec46f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the active audio format.  <a href="#a23a20e6c1144064686e03fd0650ec46f">More...</a><br/></td></tr>
<tr class="separator:a23a20e6c1144064686e03fd0650ec46f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae2022f3a37591ca01f2028e0e938e331"><td class="memItemLeft" align="right" valign="top">XV_HdmiTx1_AudioFormatType&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ae2022f3a37591ca01f2028e0e938e331">XV_HdmiTx1_GetAudioFormat</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ae2022f3a37591ca01f2028e0e938e331"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the active audio format.  <a href="#ae2022f3a37591ca01f2028e0e938e331">More...</a><br/></td></tr>
<tr class="separator:ae2022f3a37591ca01f2028e0e938e331"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a937b182eae5d5d5eefe0e7cbc0e833c7"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a937b182eae5d5d5eefe0e7cbc0e833c7">XV_HdmiTxSs1_GetAudioCtsVal</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a937b182eae5d5d5eefe0e7cbc0e833c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the Generated ACR CTS Value.  <a href="#a937b182eae5d5d5eefe0e7cbc0e833c7">More...</a><br/></td></tr>
<tr class="separator:a937b182eae5d5d5eefe0e7cbc0e833c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a58b5302d9843f58fcf1336d2a0ab9bcd"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a58b5302d9843f58fcf1336d2a0ab9bcd">XV_HdmiTxSs1_GetAudioNVal</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a58b5302d9843f58fcf1336d2a0ab9bcd"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function gets the programmed ACR N Value.  <a href="#a58b5302d9843f58fcf1336d2a0ab9bcd">More...</a><br/></td></tr>
<tr class="separator:a58b5302d9843f58fcf1336d2a0ab9bcd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad22b60a3d798ee469dcc71a04100843d"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ad22b60a3d798ee469dcc71a04100843d">XV_HdmiTx1_FRLACRStart</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ad22b60a3d798ee469dcc71a04100843d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function Starts the internal ACR module for FRL.  <a href="#ad22b60a3d798ee469dcc71a04100843d">More...</a><br/></td></tr>
<tr class="separator:ad22b60a3d798ee469dcc71a04100843d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7f1498e69d193cbd626999414e863558"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a7f1498e69d193cbd626999414e863558">XV_HdmiTx1_TMDSACRStart</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a7f1498e69d193cbd626999414e863558"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function Starts the internal ACR module for FRL.  <a href="#a7f1498e69d193cbd626999414e863558">More...</a><br/></td></tr>
<tr class="separator:a7f1498e69d193cbd626999414e863558"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aed13a9750e5630a68e868533846cd0f3"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#aed13a9750e5630a68e868533846cd0f3">XV_HdmiTx1_StartTmdsMode</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:aed13a9750e5630a68e868533846cd0f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function starts the TMDS mode.  <a href="#aed13a9750e5630a68e868533846cd0f3">More...</a><br/></td></tr>
<tr class="separator:aed13a9750e5630a68e868533846cd0f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a76d80c3b0078c28a7e0672a581588ea4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a76d80c3b0078c28a7e0672a581588ea4">XV_HdmiTx1_StartFrlTraining</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, XHdmiC_MaxFrlRate FrlRate)</td></tr>
<tr class="memdesc:a76d80c3b0078c28a7e0672a581588ea4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function starts the Fixed Rate Link Training.  <a href="#a76d80c3b0078c28a7e0672a581588ea4">More...</a><br/></td></tr>
<tr class="separator:a76d80c3b0078c28a7e0672a581588ea4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8604258acea8584d4266ff1aa6b7a47a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a8604258acea8584d4266ff1aa6b7a47a">XV_HdmiTx1_SetFrlMaxFrlRate</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, XHdmiC_MaxFrlRate MaxFrlRate)</td></tr>
<tr class="memdesc:a8604258acea8584d4266ff1aa6b7a47a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets maximum FRL Rate supported by the system.  <a href="#a8604258acea8584d4266ff1aa6b7a47a">More...</a><br/></td></tr>
<tr class="separator:a8604258acea8584d4266ff1aa6b7a47a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adf710dcbcdbe81ecb243be229e21c5b4"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#adf710dcbcdbe81ecb243be229e21c5b4">XV_HdmiTx1_ExecFrlState</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:adf710dcbcdbe81ecb243be229e21c5b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function executes the different of states of FRL.  <a href="#adf710dcbcdbe81ecb243be229e21c5b4">More...</a><br/></td></tr>
<tr class="separator:adf710dcbcdbe81ecb243be229e21c5b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a86472ba3e4497749a3b0af4fd446137d"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a86472ba3e4497749a3b0af4fd446137d">XV_HdmiTx1_FrlStreamStart</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a86472ba3e4497749a3b0af4fd446137d"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function starts FRL video stream.  <a href="#a86472ba3e4497749a3b0af4fd446137d">More...</a><br/></td></tr>
<tr class="separator:a86472ba3e4497749a3b0af4fd446137d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa70824573b3a13e9aadcc96eca9842a6"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#aa70824573b3a13e9aadcc96eca9842a6">XV_HdmiTx1_FrlStreamStop</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:aa70824573b3a13e9aadcc96eca9842a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function stops FRL video stream.  <a href="#aa70824573b3a13e9aadcc96eca9842a6">More...</a><br/></td></tr>
<tr class="separator:aa70824573b3a13e9aadcc96eca9842a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ada8afa970cedeaafee37bffd18b75f87"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ada8afa970cedeaafee37bffd18b75f87">XV_HdmiTx1_SetFrlLtp</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 Lane, XV_HdmiTx1_FrlLtpType Ltp)</td></tr>
<tr class="memdesc:ada8afa970cedeaafee37bffd18b75f87"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the link training pattern for the selected lane.  <a href="#ada8afa970cedeaafee37bffd18b75f87">More...</a><br/></td></tr>
<tr class="separator:ada8afa970cedeaafee37bffd18b75f87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adffdae706dbe4333e7f81664ccf0fd22"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#adffdae706dbe4333e7f81664ccf0fd22">XV_HdmiTx1_SetFrlActive</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, XV_HdmiTx1_FrlActiveMode Mode)</td></tr>
<tr class="memdesc:adffdae706dbe4333e7f81664ccf0fd22"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets active FRL mode.  <a href="#adffdae706dbe4333e7f81664ccf0fd22">More...</a><br/></td></tr>
<tr class="separator:adffdae706dbe4333e7f81664ccf0fd22"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a36c5a2a45c4aabd06c2e7fbdf26bb991"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a36c5a2a45c4aabd06c2e7fbdf26bb991">XV_HdmiTx1_SetFrlLanes</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 Lanes)</td></tr>
<tr class="memdesc:a36c5a2a45c4aabd06c2e7fbdf26bb991"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the number of FRL lane in operations.  <a href="#a36c5a2a45c4aabd06c2e7fbdf26bb991">More...</a><br/></td></tr>
<tr class="separator:a36c5a2a45c4aabd06c2e7fbdf26bb991"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a552e68759230c18b75c2d5510b556488"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a552e68759230c18b75c2d5510b556488">XV_HdmiTx1_FrlModeEn</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 Mode)</td></tr>
<tr class="memdesc:a552e68759230c18b75c2d5510b556488"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the FRL operation mode.  <a href="#a552e68759230c18b75c2d5510b556488">More...</a><br/></td></tr>
<tr class="separator:a552e68759230c18b75c2d5510b556488"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9ae3d651a0d9b2258415a0fcd243ee0c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a9ae3d651a0d9b2258415a0fcd243ee0c">XV_HdmiTx1_FrlReset</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 Reset)</td></tr>
<tr class="memdesc:a9ae3d651a0d9b2258415a0fcd243ee0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function resets the FRL peripheral.  <a href="#a9ae3d651a0d9b2258415a0fcd243ee0c">More...</a><br/></td></tr>
<tr class="separator:a9ae3d651a0d9b2258415a0fcd243ee0c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad03f1110009425d476e007abd30898d6"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ad03f1110009425d476e007abd30898d6">XV_HdmiTx1_FrlRate</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 FrlRate)</td></tr>
<tr class="memdesc:ad03f1110009425d476e007abd30898d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the TX core's FRL Rate and sends encoded FRL_Rate data and FFE Levels to the sink through SCDC.  <a href="#ad03f1110009425d476e007abd30898d6">More...</a><br/></td></tr>
<tr class="separator:ad03f1110009425d476e007abd30898d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8c3339f7859efd76ec6a3ee262e20caa"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a8c3339f7859efd76ec6a3ee262e20caa">XV_HdmiTx1_FrlExtVidCkeSource</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u8 Value)</td></tr>
<tr class="memdesc:a8c3339f7859efd76ec6a3ee262e20caa"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the source of the video clock enable.  <a href="#a8c3339f7859efd76ec6a3ee262e20caa">More...</a><br/></td></tr>
<tr class="separator:a8c3339f7859efd76ec6a3ee262e20caa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8f3afde27c63f277de13d600ae3118ef"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a8f3afde27c63f277de13d600ae3118ef">XV_HdmiTx1_FrlExecute</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a8f3afde27c63f277de13d600ae3118ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function executes the FRL register updates.  <a href="#a8f3afde27c63f277de13d600ae3118ef">More...</a><br/></td></tr>
<tr class="separator:a8f3afde27c63f277de13d600ae3118ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a730bc782f3ed005fbff8e45c1dbd055a"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a730bc782f3ed005fbff8e45c1dbd055a">XV_HdmiTx1_FrlTrainingInit</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a730bc782f3ed005fbff8e45c1dbd055a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function initializes FRL peripheral and sink's SCDC for FRL Training.  <a href="#a730bc782f3ed005fbff8e45c1dbd055a">More...</a><br/></td></tr>
<tr class="separator:a730bc782f3ed005fbff8e45c1dbd055a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2bf2a40cf27de9db617157942c4f901c"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a2bf2a40cf27de9db617157942c4f901c">XV_HdmiTx1_SetFrlTimer</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u32 Milliseconds)</td></tr>
<tr class="memdesc:a2bf2a40cf27de9db617157942c4f901c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the timer of TX Core's FRL peripheral.  <a href="#a2bf2a40cf27de9db617157942c4f901c">More...</a><br/></td></tr>
<tr class="separator:a2bf2a40cf27de9db617157942c4f901c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5c81c3da135fd69e74aa106dadce0ca4"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a5c81c3da135fd69e74aa106dadce0ca4">XV_HdmiTx1_SetFrlTimerClockCycles</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, u32 ClockCycles)</td></tr>
<tr class="memdesc:a5c81c3da135fd69e74aa106dadce0ca4"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the timer of TX Core's FRL peripheral in clock cycles.  <a href="#a5c81c3da135fd69e74aa106dadce0ca4">More...</a><br/></td></tr>
<tr class="separator:a5c81c3da135fd69e74aa106dadce0ca4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abe9d06ce9943cedc448f905806cbc6a2"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#abe9d06ce9943cedc448f905806cbc6a2">XV_HdmiTx1_GetFrlTimer</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:abe9d06ce9943cedc448f905806cbc6a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function returns the remaining value of the timer of TX Core's FRL peripheral.  <a href="#abe9d06ce9943cedc448f905806cbc6a2">More...</a><br/></td></tr>
<tr class="separator:abe9d06ce9943cedc448f905806cbc6a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aae90d7c942d0f3c605396316c25ad28e"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#aae90d7c942d0f3c605396316c25ad28e">XV_HdmiTx1_SetFrl10MicroSecondsTimer</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:aae90d7c942d0f3c605396316c25ad28e"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the timer of TX Core's FRL peripheral for 10 Microseconds.  <a href="#aae90d7c942d0f3c605396316c25ad28e">More...</a><br/></td></tr>
<tr class="separator:aae90d7c942d0f3c605396316c25ad28e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a29aa29c3d4533cd302e0ef543a8668f2"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a29aa29c3d4533cd302e0ef543a8668f2">XV_HdmiTx1_SetFrlWrongLtp</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a29aa29c3d4533cd302e0ef543a8668f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sets the core to send out wrong LTP on one of the channel to prevent link training from passing.  <a href="#a29aa29c3d4533cd302e0ef543a8668f2">More...</a><br/></td></tr>
<tr class="separator:a29aa29c3d4533cd302e0ef543a8668f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a05cd1decff0891fe0e51fa17f4230407"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a05cd1decff0891fe0e51fa17f4230407">XV_HdmiTx1_ClearFrlWrongLtp</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a05cd1decff0891fe0e51fa17f4230407"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function clears the debugging flag which would have prevented the core from sending out correct LTP.  <a href="#a05cd1decff0891fe0e51fa17f4230407">More...</a><br/></td></tr>
<tr class="separator:a05cd1decff0891fe0e51fa17f4230407"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4623f1c32afecde613bfb2c4517597b1"><td class="memItemLeft" align="right" valign="top">u8 *&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a4623f1c32afecde613bfb2c4517597b1">XV_HdmiTx1_GetScdcEdRegisters</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:a4623f1c32afecde613bfb2c4517597b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads the CED and RSED registers from the sink and returns the pointer to the data structure which stores the CED related readings (from SCDC register 0x50 to 0x5A).  <a href="#a4623f1c32afecde613bfb2c4517597b1">More...</a><br/></td></tr>
<tr class="separator:a4623f1c32afecde613bfb2c4517597b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac0969e712c2e4170732589e66359f592"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ac0969e712c2e4170732589e66359f592">XV_HdmiTx1_Start</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ac0969e712c2e4170732589e66359f592"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function starts the HDMI TX core.  <a href="#ac0969e712c2e4170732589e66359f592">More...</a><br/></td></tr>
<tr class="separator:ac0969e712c2e4170732589e66359f592"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac338e05672272398dfcd6748dd92da1a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ac338e05672272398dfcd6748dd92da1a">XV_HdmiTx1_Stop</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:ac338e05672272398dfcd6748dd92da1a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function stops the HDMI TX core.  <a href="#ac338e05672272398dfcd6748dd92da1a">More...</a><br/></td></tr>
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<tr class="memitem:af29db67dfae3a2ae507640836c23847a"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#af29db67dfae3a2ae507640836c23847a">XV_HdmiTx1_SelfTest</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
<tr class="memdesc:af29db67dfae3a2ae507640836c23847a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function reads ID of HDMI TX PIO peripheral.  <a href="#af29db67dfae3a2ae507640836c23847a">More...</a><br/></td></tr>
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<tr class="memitem:a1fde82d7e35ed99e6842e1f33ba09a3b"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#a1fde82d7e35ed99e6842e1f33ba09a3b">XV_HdmiTx1_IntrHandler</a> (void *InstancePtr)</td></tr>
<tr class="memdesc:a1fde82d7e35ed99e6842e1f33ba09a3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is the interrupt handler for the HDMI TX driver.  <a href="#a1fde82d7e35ed99e6842e1f33ba09a3b">More...</a><br/></td></tr>
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<tr class="memitem:ab5ebe4123d67f311237f44d4db7fbb99"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx1_8h.html#ab5ebe4123d67f311237f44d4db7fbb99">XV_HdmiTx1_SetCallback</a> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, <a class="el" href="xv__hdmitx1_8h.html#af9b30d0cba10a37e4719114fe400ea64">XV_HdmiTx1_HandlerType</a> HandlerType, void *CallbackFunc, void *CallbackRef)</td></tr>
<tr class="memdesc:ab5ebe4123d67f311237f44d4db7fbb99"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function installs an asynchronous callback function for the given HandlerType:  <a href="#ab5ebe4123d67f311237f44d4db7fbb99">More...</a><br/></td></tr>
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XV_HdmiC_VideoTimingExtMeta *&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiTx1_GetVidTimingExtMeta</b> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
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XV_HdmiC_SrcProdDescIF *&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiTx1_GetSrcProdDescIF</b> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr)</td></tr>
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void&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiTx1_GenerateVideoTimingExtMetaIF</b> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, XV_HdmiC_VideoTimingExtMeta *ExtMeta)</td></tr>
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void&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiTx1_GenerateCustomVideoTimingExtMetaIF</b> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, XV_HdmiC_VideoTimingExtMeta *ExtMeta, u16 Sync, u16 DataSetLen)</td></tr>
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void&#160;</td><td class="memItemRight" valign="bottom"><b>XV_HdmiTx1_GenerateSrcProdDescInfoframe</b> (<a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *InstancePtr, XV_HdmiC_SrcProdDescIF *SpdIfPtr)</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ac80822fe192ddd125e321cdf4c9d4608"></a>
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          <td class="memname">#define XV_HdmiTx1_AudioDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a279874e2cee1de19fee34f5f25fe4198">XV_HDMITX1_AUD_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a0b6ca194e0811b7201545d206d1a49e3">XV_HDMITX1_AUD_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a279874e2cee1de19fee34f5f25fe4198"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a279874e2cee1de19fee34f5f25fe4198">XV_HDMITX1_AUD_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUD_CTRL_CLR_OFFSET</div><div class="ttdoc">AUD Control Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:469</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a0b6ca194e0811b7201545d206d1a49e3"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a0b6ca194e0811b7201545d206d1a49e3">XV_HDMITX1_AUD_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_AUD_CTRL_RUN_MASK</div><div class="ttdoc">AUD Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:483</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
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<p>This macro disables audio in HDMI TX core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#ac80822fe192ddd125e321cdf4c9d4608" title="This macro disables audio in HDMI TX core. ">XV_HdmiTx1_AudioDisable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx1_8h.html#abaf1a4638cb906d3ead0e42630727ad1">XV_HdmiTx1_SetDviMode()</a>.</p>

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<a class="anchor" id="a885cea7ad25eb7470e839cbe329b8ec4"></a>
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          <td class="memname">#define XV_HdmiTx1_AuxDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#add021f22d0ef7e0de595b74f105d4572">XV_HDMITX1_AUX_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_add021f22d0ef7e0de595b74f105d4572"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#add021f22d0ef7e0de595b74f105d4572">XV_HDMITX1_AUX_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_RUN_MASK</div><div class="ttdoc">AUX Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:378</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a93a082440892ddad44f45085a507d526"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_CLR_OFFSET</div><div class="ttdoc">AUX Control Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:360</div></div>
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<p>This macro disables the HDMI TX Auxiliary (AUX) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a885cea7ad25eb7470e839cbe329b8ec4" title="This macro disables the HDMI TX Auxiliary (AUX) peripheral. ">XV_HdmiTx1_AuxDisable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>, <a class="el" href="xv__hdmitx1_8h.html#aa70824573b3a13e9aadcc96eca9842a6">XV_HdmiTx1_FrlStreamStop()</a>, and <a class="el" href="xv__hdmitx1_8h.html#abaf1a4638cb906d3ead0e42630727ad1">XV_HdmiTx1_SetDviMode()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_AuxIntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a0f0047db6451a68373fa03364980db22">XV_HDMITX1_AUX_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a0f0047db6451a68373fa03364980db22"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a0f0047db6451a68373fa03364980db22">XV_HDMITX1_AUX_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_IE_MASK</div><div class="ttdoc">AUX Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:379</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a93a082440892ddad44f45085a507d526"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_CLR_OFFSET</div><div class="ttdoc">AUX Control Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:360</div></div>
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<p>This macro disables interrupt in the HDMI TX AUX peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a0c8aaaa8fc3e83d9bbfb3cfd4c32cae0" title="This macro disables interrupt in the HDMI TX AUX peripheral. ">XV_HdmiTx1_AuxIntrDisable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#aa70824573b3a13e9aadcc96eca9842a6">XV_HdmiTx1_FrlStreamStop()</a>.</p>

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<a class="anchor" id="aeefc5a50cd7f61f65466eec26592b3c4"></a>
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          <td class="memname">#define XV_HdmiTx1_AuxIntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a0f0047db6451a68373fa03364980db22">XV_HDMITX1_AUX_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a97406fdf0b5b815f1a99e48f9f769ab9"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_SET_OFFSET</div><div class="ttdoc">AUX Control Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:357</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a0f0047db6451a68373fa03364980db22"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a0f0047db6451a68373fa03364980db22">XV_HDMITX1_AUX_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_IE_MASK</div><div class="ttdoc">AUX Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:379</div></div>
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<p>This macro enables interrupt in the HDMI TX AUX peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#aeefc5a50cd7f61f65466eec26592b3c4" title="This macro enables interrupt in the HDMI TX AUX peripheral. ">XV_HdmiTx1_AuxIntrEnable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a86472ba3e4497749a3b0af4fd446137d">XV_HdmiTx1_FrlStreamStart()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_Bridge_pixel</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
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        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (SetClr) { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a648102aabd55a2e9475005867d63dd6e">XV_HDMITX1_PIO_OUT_BRIDGE_PIXEL_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a648102aabd55a2e9475005867d63dd6e">XV_HDMITX1_PIO_OUT_BRIDGE_PIXEL_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a34819a1c42353de5eec449bc38c93efc"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_CLR_OFFSET</div><div class="ttdoc">PIO Out Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:153</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a648102aabd55a2e9475005867d63dd6e"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a648102aabd55a2e9475005867d63dd6e">XV_HDMITX1_PIO_OUT_BRIDGE_PIXEL_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_BRIDGE_PIXEL_MASK</div><div class="ttdoc">PIO Out Bridge_Pixel repeat mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:231</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a916d49f0a22d9ef6e369ff80353e00af"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_SET_OFFSET</div><div class="ttdoc">PIO Out Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:150</div></div>
</div><!-- fragment -->
<p>This macro controls the Pixel Repeat mode for video bridge. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either enable or disable the Pixel Repitition Support.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a112885de6b7be79d903f1c8abee64161" title="This macro controls the Pixel Repeat mode for video bridge. ">XV_HdmiTx1_Bridge_pixel(XV_HdmiTx1 *InstancePtr, u8 SetClr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_Bridge_yuv420</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (SetClr) { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#afcb960eb73caed51fff7e1028e0d3a11">XV_HDMITX1_PIO_OUT_BRIDGE_YUV420_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#afcb960eb73caed51fff7e1028e0d3a11">XV_HDMITX1_PIO_OUT_BRIDGE_YUV420_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a34819a1c42353de5eec449bc38c93efc"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_CLR_OFFSET</div><div class="ttdoc">PIO Out Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:153</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a916d49f0a22d9ef6e369ff80353e00af"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_SET_OFFSET</div><div class="ttdoc">PIO Out Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:150</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_afcb960eb73caed51fff7e1028e0d3a11"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#afcb960eb73caed51fff7e1028e0d3a11">XV_HDMITX1_PIO_OUT_BRIDGE_YUV420_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_BRIDGE_YUV420_MASK</div><div class="ttdoc">PIO Out Bridge_YUV420 mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:228</div></div>
</div><!-- fragment -->
<p>This macro controls the YUV420 mode for video bridge. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either enable or disable the YUV 420 Support.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a7af7805735f505cdea41cfbbf8bea17b" title="This macro controls the YUV420 mode for video bridge. ">XV_HdmiTx1_Bridge_yuv420(XV_HdmiTx1 *InstancePtr, u8 SetClr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_ClearMode</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a4ce35ba56d898dd0b26cc1466d7ff9e6">XV_HDMITX1_PIO_OUT_MODE_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a34819a1c42353de5eec449bc38c93efc"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_CLR_OFFSET</div><div class="ttdoc">PIO Out Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:153</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a4ce35ba56d898dd0b26cc1466d7ff9e6"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a4ce35ba56d898dd0b26cc1466d7ff9e6">XV_HDMITX1_PIO_OUT_MODE_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_MODE_MASK</div><div class="ttdoc">PIO Out Mode mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:197</div></div>
</div><!-- fragment -->
<p>This macro clears the mode bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a4ed1526a4760bbcb4b978ff021fbc360" title="This macro clears the mode bit. ">XV_HdmiTx1_ClearMode(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#abaf1a4638cb906d3ead0e42630727ad1">XV_HdmiTx1_SetDviMode()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_DdcDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a09105460882cbec545e9ef4fa49b72ae">XV_HDMITX1_DDC_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a7ff97e413ac155c87891bc822fa79213">XV_HDMITX1_DDC_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a09105460882cbec545e9ef4fa49b72ae"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a09105460882cbec545e9ef4fa49b72ae">XV_HDMITX1_DDC_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_DDC_CTRL_CLR_OFFSET</div><div class="ttdoc">DDC Control Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:295</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a7ff97e413ac155c87891bc822fa79213"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a7ff97e413ac155c87891bc822fa79213">XV_HDMITX1_DDC_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_DDC_CTRL_RUN_MASK</div><div class="ttdoc">DDC Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:309</div></div>
</div><!-- fragment -->
<p>This macro disables the HDMI TX Display Data Channel (DDC) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a48c24836f4ff579b8bf3ed1dfc298747" title="This macro disables the HDMI TX Display Data Channel (DDC) peripheral. ">XV_HdmiTx1_DdcDisable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>, <a class="el" href="xv__hdmitx1_8h.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_DdcEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a07043f2b7e7ddb3ba0f27b893e938ed2">XV_HDMITX1_DDC_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a7ff97e413ac155c87891bc822fa79213">XV_HDMITX1_DDC_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a07043f2b7e7ddb3ba0f27b893e938ed2"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a07043f2b7e7ddb3ba0f27b893e938ed2">XV_HDMITX1_DDC_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_DDC_CTRL_SET_OFFSET</div><div class="ttdoc">DDC Control Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:292</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a7ff97e413ac155c87891bc822fa79213"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a7ff97e413ac155c87891bc822fa79213">XV_HDMITX1_DDC_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_DDC_CTRL_RUN_MASK</div><div class="ttdoc">DDC Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:309</div></div>
</div><!-- fragment -->
<p>This macro enables the HDMI TX Display Data Channel (DDC) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#aa2bd58dc021ee4fe7b52eca1125f39b6" title="This macro enables the HDMI TX Display Data Channel (DDC) peripheral. ">XV_HdmiTx1_DdcEnable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_DdcIntrClear</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a76a8d1762bfc7aafed3ae667630f47d6">XV_HDMITX1_DDC_STA_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a74458333d15b366f123b04bb3fa44042">XV_HDMITX1_DDC_STA_IRQ_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a74458333d15b366f123b04bb3fa44042"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a74458333d15b366f123b04bb3fa44042">XV_HDMITX1_DDC_STA_IRQ_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_DDC_STA_IRQ_MASK</div><div class="ttdoc">DDC Status IRQ mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:323</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a76a8d1762bfc7aafed3ae667630f47d6"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a76a8d1762bfc7aafed3ae667630f47d6">XV_HDMITX1_DDC_STA_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_DDC_STA_OFFSET</div><div class="ttdoc">DDC Status Register * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:298</div></div>
</div><!-- fragment -->
<p>This macro clears HDMI TX DDC interrupt. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a1a4bb321f73f08e71204821bb3c68b3d" title="This macro clears HDMI TX DDC interrupt. ">XV_HdmiTx1_DdcIntrClear(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

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<a class="anchor" id="a0a0262addeb5640e4b2d681202559056"></a>
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          <td class="memname">#define XV_HdmiTx1_DdcIntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a09105460882cbec545e9ef4fa49b72ae">XV_HDMITX1_DDC_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a5eb95f04ded48dfbc6d9b1895d86ba6e">XV_HDMITX1_DDC_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a5eb95f04ded48dfbc6d9b1895d86ba6e"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a5eb95f04ded48dfbc6d9b1895d86ba6e">XV_HDMITX1_DDC_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_DDC_CTRL_IE_MASK</div><div class="ttdoc">DDC Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:310</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a09105460882cbec545e9ef4fa49b72ae"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a09105460882cbec545e9ef4fa49b72ae">XV_HDMITX1_DDC_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_DDC_CTRL_CLR_OFFSET</div><div class="ttdoc">DDC Control Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:295</div></div>
</div><!-- fragment -->
<p>This macro disables interrupt in the HDMI TX DDC peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a0a0262addeb5640e4b2d681202559056" title="This macro disables interrupt in the HDMI TX DDC peripheral. ">XV_HdmiTx1_DdcIntrDisable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>.</p>

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<a class="anchor" id="a8e3011104d6800a0bf73887c3ad5cad5"></a>
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      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiTx1_DdcIntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a07043f2b7e7ddb3ba0f27b893e938ed2">XV_HDMITX1_DDC_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a5eb95f04ded48dfbc6d9b1895d86ba6e">XV_HDMITX1_DDC_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a07043f2b7e7ddb3ba0f27b893e938ed2"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a07043f2b7e7ddb3ba0f27b893e938ed2">XV_HDMITX1_DDC_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_DDC_CTRL_SET_OFFSET</div><div class="ttdoc">DDC Control Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:292</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a5eb95f04ded48dfbc6d9b1895d86ba6e"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a5eb95f04ded48dfbc6d9b1895d86ba6e">XV_HDMITX1_DDC_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_DDC_CTRL_IE_MASK</div><div class="ttdoc">DDC Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:310</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
</div><!-- fragment -->
<p>This macro enables interrupt in the HDMI TX DDC peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a8e3011104d6800a0bf73887c3ad5cad5" title="This macro enables interrupt in the HDMI TX DDC peripheral. ">XV_HdmiTx1_DdcIntrEnable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="a9654f55c13fef03588ff7d4c870fc37a"></a>
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          <td class="memname">#define XV_HdmiTx1_DscControl</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (SetClr) { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">                XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#ac0c1dc603ec9771599bd82313b870bde">XV_HDMITX1_AUX_CTRL_DSC_EN_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">                XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#ac0c1dc603ec9771599bd82313b870bde">XV_HDMITX1_AUX_CTRL_DSC_EN_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_ac0c1dc603ec9771599bd82313b870bde"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#ac0c1dc603ec9771599bd82313b870bde">XV_HDMITX1_AUX_CTRL_DSC_EN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_DSC_EN_MASK</div><div class="ttdoc">AUX Control DSC En mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:388</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a97406fdf0b5b815f1a99e48f9f769ab9"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_SET_OFFSET</div><div class="ttdoc">AUX Control Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:357</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a93a082440892ddad44f45085a507d526"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_CLR_OFFSET</div><div class="ttdoc">AUX Control Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:360</div></div>
</div><!-- fragment -->
<p>This macro allows enabling/disabling of DSC in HDMI-TX. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either enable or disable the DSC</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a9654f55c13fef03588ff7d4c870fc37a" title="This macro allows enabling/disabling of DSC in HDMI-TX. ">XV_HdmiTx1_DscControl(XV_HdmiTx1 *InstancePtr, u8 SetClr)</a> </dd></dl>

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<a class="anchor" id="a725ca58c53140f1988f01a8905b988e9"></a>
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          <td class="memname">#define XV_HdmiTx1_DynHdr_Control</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (InstancePtr-&gt;Config.DynHdr) { \</div>
<div class="line">                if (SetClr) { <a class="code" href="xv__hdmitx1_8h.html#ae2165f794a177f55510c8352ecc9a98b">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1_8h.html#ae2165f794a177f55510c8352ecc9a98b">			XV_HdmiTx1_DynHdr_DM_Enable</a>(InstancePtr); <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">			XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#aa238147ea10632c793db777b956f97ea">XV_HDMITX1_AUX_CTRL_DYNHDR_EN_MASK</a>)); \</div>
<div class="line">                } \</div>
<div class="line">                else { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">			XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#aa238147ea10632c793db777b956f97ea">XV_HDMITX1_AUX_CTRL_DYNHDR_EN_MASK</a>)); <a class="code" href="xv__hdmitx1_8h.html#a18b2a682a5a6928c3cdee2456563227c">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1_8h.html#a18b2a682a5a6928c3cdee2456563227c">			XV_HdmiTx1_DynHdr_DM_Disable</a>(InstancePtr); \</div>
<div class="line">                } \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_aa238147ea10632c793db777b956f97ea"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#aa238147ea10632c793db777b956f97ea">XV_HDMITX1_AUX_CTRL_DYNHDR_EN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_DYNHDR_EN_MASK</div><div class="ttdoc">AUX Control Enable Dynamic HDR mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:384</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a97406fdf0b5b815f1a99e48f9f769ab9"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_SET_OFFSET</div><div class="ttdoc">AUX Control Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:357</div></div>
<div class="ttc" id="xv__hdmitx1_8h_html_ae2165f794a177f55510c8352ecc9a98b"><div class="ttname"><a href="xv__hdmitx1_8h.html#ae2165f794a177f55510c8352ecc9a98b">XV_HdmiTx1_DynHdr_DM_Enable</a></div><div class="ttdeci">#define XV_HdmiTx1_DynHdr_DM_Enable(InstancePtr)</div><div class="ttdoc">This macro enables the data mover for Dynamic HDR in HDMI Tx. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1.h:892</div></div>
<div class="ttc" id="xv__hdmitx1_8h_html_a18b2a682a5a6928c3cdee2456563227c"><div class="ttname"><a href="xv__hdmitx1_8h.html#a18b2a682a5a6928c3cdee2456563227c">XV_HdmiTx1_DynHdr_DM_Disable</a></div><div class="ttdeci">#define XV_HdmiTx1_DynHdr_DM_Disable(InstancePtr)</div><div class="ttdoc">This macro disables the data mover for Dynamic HDR in HDMI Tx. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1.h:914</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a93a082440892ddad44f45085a507d526"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_CLR_OFFSET</div><div class="ttdoc">AUX Control Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:360</div></div>
</div><!-- fragment -->
<p>This macro allows enabling/disabling of Dynamic HDR in HDMI Tx. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either enable or disable the Dynamic HDR</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XV_HdmiTx1_DynHdrControl(XV_HdmiTx1 *InstancePtr, u8 SetClr) </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_DynHdr_DM_Disable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (InstancePtr-&gt;Config.DynHdr) { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    <a class="code" href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a>, \</div>
<div class="line">                                    <a class="code" href="xv__hdmitx1__hw_8h.html#abe4e12802e1167c1761c54d00083dad6">XV_HDMITX1_PIO_OUT_DYN_HDR_DM_EN_MASK</a>); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a34819a1c42353de5eec449bc38c93efc"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_CLR_OFFSET</div><div class="ttdoc">PIO Out Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:153</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_abe4e12802e1167c1761c54d00083dad6"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#abe4e12802e1167c1761c54d00083dad6">XV_HDMITX1_PIO_OUT_DYN_HDR_DM_EN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_DYN_HDR_DM_EN_MASK</div><div class="ttdoc">PIO Out Dynamic HDR Data Mover Enable. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:249</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
</div><!-- fragment -->
<p>This macro disables the data mover for Dynamic HDR in HDMI Tx. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a18b2a682a5a6928c3cdee2456563227c" title="This macro disables the data mover for Dynamic HDR in HDMI Tx. ">XV_HdmiTx1_DynHdr_DM_Disable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#aa70824573b3a13e9aadcc96eca9842a6">XV_HdmiTx1_FrlStreamStop()</a>.</p>

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<a class="anchor" id="ae2165f794a177f55510c8352ecc9a98b"></a>
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          <td class="memname">#define XV_HdmiTx1_DynHdr_DM_Enable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (InstancePtr-&gt;Config.DynHdr) { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    <a class="code" href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a>, \</div>
<div class="line">                                    <a class="code" href="xv__hdmitx1__hw_8h.html#abe4e12802e1167c1761c54d00083dad6">XV_HDMITX1_PIO_OUT_DYN_HDR_DM_EN_MASK</a>); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_abe4e12802e1167c1761c54d00083dad6"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#abe4e12802e1167c1761c54d00083dad6">XV_HDMITX1_PIO_OUT_DYN_HDR_DM_EN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_DYN_HDR_DM_EN_MASK</div><div class="ttdoc">PIO Out Dynamic HDR Data Mover Enable. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:249</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a916d49f0a22d9ef6e369ff80353e00af"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_SET_OFFSET</div><div class="ttdoc">PIO Out Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:150</div></div>
</div><!-- fragment -->
<p>This macro enables the data mover for Dynamic HDR in HDMI Tx. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#ae2165f794a177f55510c8352ecc9a98b" title="This macro enables the data mover for Dynamic HDR in HDMI Tx. ">XV_HdmiTx1_DynHdr_DM_Enable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a86472ba3e4497749a3b0af4fd446137d">XV_HdmiTx1_FrlStreamStart()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_DynHdr_FAPA_Control</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (InstancePtr-&gt;Config.DynHdr) { \</div>
<div class="line">                if (SetClr) { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">			XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#ae12a08f10a443b8e49a07731cabc4ac7">XV_HDMITX1_AUX_CTRL_DYNHDR_FAPA_LOC_MASK</a>)); \</div>
<div class="line">                } \</div>
<div class="line">                else { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">			XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#ae12a08f10a443b8e49a07731cabc4ac7">XV_HDMITX1_AUX_CTRL_DYNHDR_FAPA_LOC_MASK</a>)); \</div>
<div class="line">                } \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_ae12a08f10a443b8e49a07731cabc4ac7"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#ae12a08f10a443b8e49a07731cabc4ac7">XV_HDMITX1_AUX_CTRL_DYNHDR_FAPA_LOC_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_DYNHDR_FAPA_LOC_MASK</div><div class="ttdoc">AUX Control FAPA Location value mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:387</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a97406fdf0b5b815f1a99e48f9f769ab9"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_SET_OFFSET</div><div class="ttdoc">AUX Control Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:357</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a93a082440892ddad44f45085a507d526"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_CLR_OFFSET</div><div class="ttdoc">AUX Control Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:360</div></div>
</div><!-- fragment -->
<p>This macro allows enabling/disabling of FAPA Location Dynamic HDR in HDMI Tx. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value for FAPA location.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XV_HdmiTx1_DynHdr_FAPA_Control(<a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> *InstancePtr, u8 SetClr) </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_DynHdr_GetReadStatus</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                           <a class="code" href="xv__hdmitx1__hw_8h.html#a14dcc9b57dc6ff4a5d43c9df86e54723">XV_HDMITX1_AUX_STA_OFFSET</a>) &amp; <a class="code" href="xv__hdmitx1__hw_8h.html#a1a0133865be039e932ce2e7148d597f6">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#a1a0133865be039e932ce2e7148d597f6">			XV_HDMITX1_AUX_DYNHDR_RD_STS_MASK</a>);</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a1a0133865be039e932ce2e7148d597f6"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a1a0133865be039e932ce2e7148d597f6">XV_HDMITX1_AUX_DYNHDR_RD_STS_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_DYNHDR_RD_STS_MASK</div><div class="ttdoc">AUX Status Dynamic HDR read response. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:420</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a374eee1fb3e859285b0e6deeb5cd3b7b"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a></div><div class="ttdeci">#define XV_HdmiTx1_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:742</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a14dcc9b57dc6ff4a5d43c9df86e54723"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a14dcc9b57dc6ff4a5d43c9df86e54723">XV_HDMITX1_AUX_STA_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_STA_OFFSET</div><div class="ttdoc">AUX Status Register * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:363</div></div>
</div><!-- fragment -->
<p>This macro gets the read status of Data Mover for Dynamic HDR in HDMI Tx. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>u32 val - 0 means ok else memory read error</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xv__hdmitx1_8h.html#adfe9f81467882df525e80e6e0da2eeb4" title="This macro gets the read status of Data Mover for Dynamic HDR in HDMI Tx. ">XV_HdmiTx1_DynHdr_GetReadStatus(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="ad1d2c212b436c956d75a234da2eaaf81"></a>
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          <td class="memname">#define XV_HdmiTx1_DynHdr_GOF_Control</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (InstancePtr-&gt;Config.DynHdr) { \</div>
<div class="line">                if (SetClr) { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">			XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a065623d68e18b9a4be22479637156a58">XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_EN_MASK</a>)); \</div>
<div class="line">                } \</div>
<div class="line">                else { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">			XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a065623d68e18b9a4be22479637156a58">XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_EN_MASK</a>)); \</div>
<div class="line">                } \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a065623d68e18b9a4be22479637156a58"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a065623d68e18b9a4be22479637156a58">XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_EN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_EN_MASK</div><div class="ttdoc">AUX Control Enable Graphic Overlay Flag mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:385</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a97406fdf0b5b815f1a99e48f9f769ab9"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_SET_OFFSET</div><div class="ttdoc">AUX Control Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:357</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a93a082440892ddad44f45085a507d526"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_CLR_OFFSET</div><div class="ttdoc">AUX Control Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:360</div></div>
</div><!-- fragment -->
<p>This macro allows enabling/disabling of GOF Dynamic HDR in HDMI Tx. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either enable or disable the GOF (Graphics Overlay Flag)</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XV_HdmiTx1_DynHdr_GOF_Control(<a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> *InstancePtr, u8 SetClr) </dd></dl>

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<a class="anchor" id="ade55c5cc63a3f03ea6d31044ae6ac6dc"></a>
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<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiTx1_DynHdr_GOFVal_Control</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (InstancePtr-&gt;Config.DynHdr) { \</div>
<div class="line">                if (SetClr) { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">			XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a11430497f5fdcaf795ac6aa779e45322">XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_VAL_MASK</a>)); \</div>
<div class="line">                } \</div>
<div class="line">                else { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">			XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a11430497f5fdcaf795ac6aa779e45322">XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_VAL_MASK</a>)); \</div>
<div class="line">                } \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a11430497f5fdcaf795ac6aa779e45322"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a11430497f5fdcaf795ac6aa779e45322">XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_VAL_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_DYNHDR_GOF_VAL_MASK</div><div class="ttdoc">AUX Control Graphic Overlay Flag value mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:386</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a97406fdf0b5b815f1a99e48f9f769ab9"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_SET_OFFSET</div><div class="ttdoc">AUX Control Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:357</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a93a082440892ddad44f45085a507d526"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_CLR_OFFSET</div><div class="ttdoc">AUX Control Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:360</div></div>
</div><!-- fragment -->
<p>This macro allows set/clear of GOF Value Dynamic HDR in HDMI Tx. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either set or clear the GOF (Graphics Overlay Flag) Value</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XV_HdmiTx1_DynHdr_GOFVal_Control(<a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> *InstancePtr, u8 SetClr) </dd></dl>

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<a class="anchor" id="a8e5aac8b73e29cead73018767a441003"></a>
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          <td class="memname">#define XV_HdmiTx1_DynHdr_MTW_Clear</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        u32 val; \</div>
<div class="line">        if (InstancePtr-&gt;Config.DynHdr) { \</div>
<div class="line">                val = <a class="code" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                         <a class="code" href="xv__hdmitx1__hw_8h.html#a14dcc9b57dc6ff4a5d43c9df86e54723">XV_HDMITX1_AUX_STA_OFFSET</a>); \</div>
<div class="line">                val |= <a class="code" href="xv__hdmitx1__hw_8h.html#a79b2893e2ea896e0def9b7b0685a5072">XV_HDMITX1_AUX_STA_DYNHDR_MTW_MASK</a>; <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a14dcc9b57dc6ff4a5d43c9df86e54723">XV_HDMITX1_AUX_STA_OFFSET</a>), \</div>
<div class="line">                                    val); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a79b2893e2ea896e0def9b7b0685a5072"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a79b2893e2ea896e0def9b7b0685a5072">XV_HDMITX1_AUX_STA_DYNHDR_MTW_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_STA_DYNHDR_MTW_MASK</div><div class="ttdoc">AUX Status Dynamic HDR MTW started. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:416</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a374eee1fb3e859285b0e6deeb5cd3b7b"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a></div><div class="ttdeci">#define XV_HdmiTx1_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:742</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a14dcc9b57dc6ff4a5d43c9df86e54723"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a14dcc9b57dc6ff4a5d43c9df86e54723">XV_HDMITX1_AUX_STA_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_STA_OFFSET</div><div class="ttdoc">AUX Status Register * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:363</div></div>
</div><!-- fragment -->
<p>This macro allows to set the MTW bit to clear it for Dynamic HDR in HDMI Tx. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a8e5aac8b73e29cead73018767a441003" title="This macro allows to set the MTW bit to clear it for Dynamic HDR in HDMI Tx. ">XV_HdmiTx1_DynHdr_MTW_Clear(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="a5ef7d028f59c8bbeb435526b2bdb7ee6"></a>
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<div class="memproto">
      <table class="memname">
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          <td class="memname">#define XV_HdmiTx1_DynHdr_SetAddr</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Addr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (InstancePtr-&gt;Config.DynHdr) { \</div>
<div class="line">                u32 val; \</div>
<div class="line">                val = (u32)Addr; <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    <a class="code" href="xv__hdmitx1__hw_8h.html#afb66a15f24bb7fe50bd7eefa2f92c733">XV_HDMITX1_AUX_DYNHDR_ADDR_LSB_OFFSET</a>, \</div>
<div class="line">                                    val); \</div>
<div class="line">                val = (u32)(((u64)Addr &amp; 0xFFFFFFFF00000000) &gt;&gt; 32); <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    <a class="code" href="xv__hdmitx1__hw_8h.html#a40edecc0f4acd35d2e0a041a98f8051e">XV_HDMITX1_AUX_DYNHDR_ADDR_MSB_OFFSET</a>, \</div>
<div class="line">                                    val); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_afb66a15f24bb7fe50bd7eefa2f92c733"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#afb66a15f24bb7fe50bd7eefa2f92c733">XV_HDMITX1_AUX_DYNHDR_ADDR_LSB_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_DYNHDR_ADDR_LSB_OFFSET</div><div class="ttdoc">AUX Dynamic HDR Address LSB offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:373</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a40edecc0f4acd35d2e0a041a98f8051e"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a40edecc0f4acd35d2e0a041a98f8051e">XV_HDMITX1_AUX_DYNHDR_ADDR_MSB_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_DYNHDR_ADDR_MSB_OFFSET</div><div class="ttdoc">AUX Dynamic HDR Address MSB offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:374</div></div>
</div><!-- fragment -->
<p>This macro sets the buffer address for Dynamic HDR in HDMI Tx. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">Addr</td><td>is a u64 which contains the buffer address</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a5ef7d028f59c8bbeb435526b2bdb7ee6" title="This macro sets the buffer address for Dynamic HDR in HDMI Tx. ">XV_HdmiTx1_DynHdr_SetAddr(XV_HdmiTx1 *InstancePtr, u64 Addr)</a> </dd></dl>

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<a class="anchor" id="ae7239649dafa25907a4f4b8101248395"></a>
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          <td class="memname">#define XV_HdmiTx1_DynHdr_SetPacket</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">PktLen, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">PktType&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (InstancePtr-&gt;Config.DynHdr) { \</div>
<div class="line">                u32 val = (u16)PktType | \</div>
<div class="line">                ((u16)PktLen &lt;&lt; XV_HDMITX1_AUX_DYNHDR_PKT_LENGTH_SHIFT); <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    <a class="code" href="xv__hdmitx1__hw_8h.html#af1aa16a7946897669f6883d9f0532cf2">XV_HDMITX1_AUX_DYNHDR_PKT_OFFSET</a>, \</div>
<div class="line">                                    val); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af1aa16a7946897669f6883d9f0532cf2"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af1aa16a7946897669f6883d9f0532cf2">XV_HDMITX1_AUX_DYNHDR_PKT_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_DYNHDR_PKT_OFFSET</div><div class="ttdoc">AUX Dynamic HDR Packet offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:372</div></div>
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<p>This macro sets the Header packet type and length for Dynamic HDR in HDMI Tx. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">PktLength</td><td>is a u16 length of Dynamic HDR packet. </td></tr>
    <tr><td class="paramname">PktType</td><td>is a u16 Type of Dynamic HDR packet.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void XV_HdmiTx1_DynHdr_SetPacket(<a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> *InstancePtr, u16 PacketLength, u16 PacketType) </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_FSyncControl</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (SetClr) { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#acf287b290181336c53fc2c239b66a82f">XV_HDMITX1_AUX_CTRL_FYSYNC_EN_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#acf287b290181336c53fc2c239b66a82f">XV_HDMITX1_AUX_CTRL_FYSYNC_EN_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a97406fdf0b5b815f1a99e48f9f769ab9"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_SET_OFFSET</div><div class="ttdoc">AUX Control Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:357</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_acf287b290181336c53fc2c239b66a82f"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#acf287b290181336c53fc2c239b66a82f">XV_HDMITX1_AUX_CTRL_FYSYNC_EN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_FYSYNC_EN_MASK</div><div class="ttdoc">AUX Control FSync En mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:383</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a93a082440892ddad44f45085a507d526"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_CLR_OFFSET</div><div class="ttdoc">AUX Control Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:360</div></div>
</div><!-- fragment -->
<p>This macro allows enabling/disabling of FSync in HDMI Tx. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either enable or disable the VFP Event</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a1a30ec57f9a1a00ca63e9d3fdecf5204" title="This macro allows enabling/disabling of FSync in HDMI Tx. ">XV_HdmiTx1_FSyncControl(XV_HdmiTx1 *InstancePtr, u8 SetClr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_GetAudioChannels</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;(InstancePtr)-&gt;Stream.Audio.Channels</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro provides the active audio channels. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Audio channels </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_GetMode</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#aef14faec6d7dec76359597de87c027e1">XV_HDMITX1_PIO_OUT_OFFSET</a>)) &amp; \</div>
<div class="line">        (<a class="code" href="xv__hdmitx1__hw_8h.html#a4ce35ba56d898dd0b26cc1466d7ff9e6">XV_HDMITX1_PIO_OUT_MODE_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a4ce35ba56d898dd0b26cc1466d7ff9e6"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a4ce35ba56d898dd0b26cc1466d7ff9e6">XV_HDMITX1_PIO_OUT_MODE_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_MODE_MASK</div><div class="ttdoc">PIO Out Mode mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:197</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_aef14faec6d7dec76359597de87c027e1"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#aef14faec6d7dec76359597de87c027e1">XV_HDMITX1_PIO_OUT_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_OFFSET</div><div class="ttdoc">PIO Out Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:147</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a374eee1fb3e859285b0e6deeb5cd3b7b"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a></div><div class="ttdeci">#define XV_HdmiTx1_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:742</div></div>
</div><!-- fragment -->
<p>This macro provides the current mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Current mode. 0 = DVI 1 = HDMI</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u8 <a class="el" href="xv__hdmitx1_8h.html#a105919aa6ac08f5ca806441ca1199b36" title="This macro provides the current mode. ">XV_HdmiTx1_GetMode(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_GetPixelPackingPhase</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(((<a class="code" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                              (<a class="code" href="xv__hdmitx1__hw_8h.html#ab20b6e84abcd0378fbc8e17282eacb16">XV_HDMITX1_PIO_IN_OFFSET</a>))) &gt;&gt; \</div>
<div class="line">          (<a class="code" href="xv__hdmitx1__hw_8h.html#ada3d9d45b3dfcc1f6ed0bf48ee626a4b">XV_HDMITX1_PIO_IN_PPP_SHIFT</a>)) &amp; \</div>
<div class="line">         (<a class="code" href="xv__hdmitx1__hw_8h.html#a0ebc15cfa04faafb28f8ffbf75ae033a">XV_HDMITX1_PIO_IN_PPP_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_ada3d9d45b3dfcc1f6ed0bf48ee626a4b"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#ada3d9d45b3dfcc1f6ed0bf48ee626a4b">XV_HDMITX1_PIO_IN_PPP_SHIFT</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_IN_PPP_SHIFT</div><div class="ttdoc">PIO In Pixel packing phase shift. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:270</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a0ebc15cfa04faafb28f8ffbf75ae033a"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a0ebc15cfa04faafb28f8ffbf75ae033a">XV_HDMITX1_PIO_IN_PPP_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_IN_PPP_MASK</div><div class="ttdoc">PIO In Pixel packing phase mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:264</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a374eee1fb3e859285b0e6deeb5cd3b7b"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a></div><div class="ttdeci">#define XV_HdmiTx1_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:742</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_ab20b6e84abcd0378fbc8e17282eacb16"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#ab20b6e84abcd0378fbc8e17282eacb16">XV_HDMITX1_PIO_IN_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_IN_OFFSET</div><div class="ttdoc">PIO In Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:159</div></div>
</div><!-- fragment -->
<p>This macro provides the current pixel packing phase. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Pixel packing phase. </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_GetSampleRate</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;(InstancePtr)-&gt;Stream.SampleRate</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro provides the current sample rate. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Sample rate</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u8 <a class="el" href="xv__hdmitx1_8h.html#a426ea58febc9ac3fdd48e9a9210ea395" title="This macro provides the current sample rate. ">XV_HdmiTx1_GetSampleRate(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_GetTime10Ms</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;(InstancePtr)-&gt;Config.AxiLiteClkFreq/100</td>
        </tr>
      </table>
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<p>This macro returns the clock cycles required to count up to 10MS with respect to AXI Lite Frequency. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XV_HdmiTX core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_GetTime1Ms</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td>&#160;&#160;&#160;(InstancePtr)-&gt;Config.AxiLiteClkFreq/1000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro returns the clock cycles required to count up to 1MS with respect to AXI Lite Frequency. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XV_HdmiTX1 core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_GetVersion</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                           (<a class="code" href="xv__hdmitx1__hw_8h.html#ab85b13706cb38b267c66b44d3533e000">XV_HDMITX1_VER_VERSION_OFFSET</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_ab85b13706cb38b267c66b44d3533e000"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#ab85b13706cb38b267c66b44d3533e000">XV_HDMITX1_VER_VERSION_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_VER_VERSION_OFFSET</div><div class="ttdoc">VER Version Register * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:81</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a374eee1fb3e859285b0e6deeb5cd3b7b"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a></div><div class="ttdeci">#define XV_HdmiTx1_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:742</div></div>
</div><!-- fragment -->
<p>This macro reads the TX version. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XV_HdmiTX1 core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

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<a class="anchor" id="a6926aebb0befff7242eceee32a5f74cb"></a>
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          <td class="memname">#define XV_HDMITX1_H_</td>
        </tr>
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<p>Prevent circular inclusions by using protection macros. </p>

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          <td class="memname">#define XV_HdmiTx1_IsMasked</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                           (<a class="code" href="xv__hdmitx1__hw_8h.html#ab6a37549bc9888ef902b62f9f0e30ef1">XV_HDMITX1_MASK_CTRL_OFFSET</a>)) &amp; \</div>
<div class="line">        (<a class="code" href="xv__hdmitx1__hw_8h.html#aa76f75af182c527f0837a8e72e07a0ab">XV_HDMITX1_MASK_CTRL_RUN_MASK</a>)</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_aa76f75af182c527f0837a8e72e07a0ab"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#aa76f75af182c527f0837a8e72e07a0ab">XV_HDMITX1_MASK_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_MASK_CTRL_RUN_MASK</div><div class="ttdoc">MASK Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:556</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_ab6a37549bc9888ef902b62f9f0e30ef1"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#ab6a37549bc9888ef902b62f9f0e30ef1">XV_HDMITX1_MASK_CTRL_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_MASK_CTRL_OFFSET</div><div class="ttdoc">MASK Control Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:533</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a374eee1fb3e859285b0e6deeb5cd3b7b"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a></div><div class="ttdeci">#define XV_HdmiTx1_ReadReg(BaseAddress, RegOffset)</div><div class="ttdoc">This macro reads a value from a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:742</div></div>
</div><!-- fragment -->
<p>This macro provides the current video mask mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Current mode. 0 = Video masking is disabled 1 = Video masking is enabled</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u8 <a class="el" href="xv__hdmitx1_8h.html#a58c3a99be0feecd24bd3835e356656a2" title="This macro provides the current video mask mode. ">XV_HdmiTx1_IsMasked(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_MaskDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">	XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a898ea3e6392a25115f070b6bd759e2c7">XV_HDMITX1_MASK_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#aa76f75af182c527f0837a8e72e07a0ab">XV_HDMITX1_MASK_CTRL_RUN_MASK</a>)); \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a898ea3e6392a25115f070b6bd759e2c7"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a898ea3e6392a25115f070b6bd759e2c7">XV_HDMITX1_MASK_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_MASK_CTRL_CLR_OFFSET</div><div class="ttdoc">MASK Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:539</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_aa76f75af182c527f0837a8e72e07a0ab"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#aa76f75af182c527f0837a8e72e07a0ab">XV_HDMITX1_MASK_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_MASK_CTRL_RUN_MASK</div><div class="ttdoc">MASK Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:556</div></div>
</div><!-- fragment -->
<p>This macro disables video mask in HDMI TX core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a2100b1d5fae612b83ca0ccfbca59d9ce" title="This macro disables video mask in HDMI TX core. ">XV_HdmiTx1_MaskDisable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

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<a class="anchor" id="ac82eb2360dcea3ef22415e7c22832d2a"></a>
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          <td class="memname">#define XV_HdmiTx1_MaskEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">	XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#ac83138bb1465d39d0f80a53700c0b884">XV_HDMITX1_MASK_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#aa76f75af182c527f0837a8e72e07a0ab">XV_HDMITX1_MASK_CTRL_RUN_MASK</a>)); \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_ac83138bb1465d39d0f80a53700c0b884"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#ac83138bb1465d39d0f80a53700c0b884">XV_HDMITX1_MASK_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_MASK_CTRL_SET_OFFSET</div><div class="ttdoc">MASK Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:536</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_aa76f75af182c527f0837a8e72e07a0ab"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#aa76f75af182c527f0837a8e72e07a0ab">XV_HDMITX1_MASK_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_MASK_CTRL_RUN_MASK</div><div class="ttdoc">MASK Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:556</div></div>
</div><!-- fragment -->
<p>This macro enables video mask in HDMI TX core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#ac82eb2360dcea3ef22415e7c22832d2a" title="This macro enables video mask in HDMI TX core. ">XV_HdmiTx1_MaskEnable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_MaskNoise</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (SetClr) { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#ac83138bb1465d39d0f80a53700c0b884">XV_HDMITX1_MASK_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a59eb379430a75238522ae45d39bfb8e7">XV_HDMITX1_MASK_CTRL_NOISE_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a898ea3e6392a25115f070b6bd759e2c7">XV_HDMITX1_MASK_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a59eb379430a75238522ae45d39bfb8e7">XV_HDMITX1_MASK_CTRL_NOISE_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_ac83138bb1465d39d0f80a53700c0b884"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#ac83138bb1465d39d0f80a53700c0b884">XV_HDMITX1_MASK_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_MASK_CTRL_SET_OFFSET</div><div class="ttdoc">MASK Control Register Set offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:536</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a59eb379430a75238522ae45d39bfb8e7"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a59eb379430a75238522ae45d39bfb8e7">XV_HDMITX1_MASK_CTRL_NOISE_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_MASK_CTRL_NOISE_MASK</div><div class="ttdoc">MASK Control Noise. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:557</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a898ea3e6392a25115f070b6bd759e2c7"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a898ea3e6392a25115f070b6bd759e2c7">XV_HDMITX1_MASK_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_MASK_CTRL_CLR_OFFSET</div><div class="ttdoc">MASK Control Register Clear offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:539</div></div>
</div><!-- fragment -->
<p>This macro enables or disables the noise in the video mask. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either enable or disable the Noise.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a5c88bd8ccdac3d52e52f7d2424a6c87a" title="This macro enables or disables the noise in the video mask. ">XV_HdmiTx1_MaskNoise(XV_HdmiTx1 *InstancePtr, u8 SetClr)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_MaskSetBlue</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a20bd10d0de6ddcc5bd6b17b3c7121d65">XV_HDMITX1_MASK_BLUE_OFFSET</a>), \</div>
<div class="line">                                    (Value)); \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a20bd10d0de6ddcc5bd6b17b3c7121d65"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a20bd10d0de6ddcc5bd6b17b3c7121d65">XV_HDMITX1_MASK_BLUE_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_MASK_BLUE_OFFSET</div><div class="ttdoc">MASK Blue Component Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:551</div></div>
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<p>This macro sets the blue component value in the video mask. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance. </td></tr>
    <tr><td class="paramname">Value</td><td></td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#ac855dfb7ad3b16fbae667da7c09ea20b" title="This macro sets the blue component value in the video mask. ">XV_HdmiTx1_MaskSetBlue(XV_HdmiTx1 *InstancePtr, u16 Value)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_MaskSetGreen</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a1cac6ccd3a3706173ed032c701e14087">XV_HDMITX1_MASK_GREEN_OFFSET</a>), \</div>
<div class="line">                                    (Value)); \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a1cac6ccd3a3706173ed032c701e14087"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a1cac6ccd3a3706173ed032c701e14087">XV_HDMITX1_MASK_GREEN_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_MASK_GREEN_OFFSET</div><div class="ttdoc">MASK Green Component Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:548</div></div>
</div><!-- fragment -->
<p>This macro sets the green component value in the video mask. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance. </td></tr>
    <tr><td class="paramname">Value</td><td></td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#ab1f3f7aa051a3fb35c1af544a57152ae" title="This macro sets the green component value in the video mask. ">XV_HdmiTx1_MaskSetGreen(XV_HdmiTx1 *InstancePtr, u16 Value)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_MaskSetRed</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Value&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a15730fa7eed0854af7219fdfecd974c1">XV_HDMITX1_MASK_RED_OFFSET</a>), \</div>
<div class="line">                                    (Value)); \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a15730fa7eed0854af7219fdfecd974c1"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a15730fa7eed0854af7219fdfecd974c1">XV_HDMITX1_MASK_RED_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_MASK_RED_OFFSET</div><div class="ttdoc">MASK Red Component Register offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:545</div></div>
</div><!-- fragment -->
<p>This macro sets the red component value in the video mask. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance. </td></tr>
    <tr><td class="paramname">Value</td><td></td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a1fb069b9cad8d5bb6eb00e951ec8ca0d" title="This macro sets the red component value in the video mask. ">XV_HdmiTx1_MaskSetRed(XV_HdmiTx1 *InstancePtr, u16 Value)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_PioDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#ab2c8c843f94dae2bf7b7050da886ee8f">XV_HDMITX1_PIO_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a7dbedee4c4749f3d28da3b493c792cb6">XV_HDMITX1_PIO_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a7dbedee4c4749f3d28da3b493c792cb6"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a7dbedee4c4749f3d28da3b493c792cb6">XV_HDMITX1_PIO_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_CTRL_RUN_MASK</div><div class="ttdoc">PIO Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:186</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_ab2c8c843f94dae2bf7b7050da886ee8f"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#ab2c8c843f94dae2bf7b7050da886ee8f">XV_HDMITX1_PIO_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_CTRL_CLR_OFFSET</div><div class="ttdoc">PIO Control Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:141</div></div>
</div><!-- fragment -->
<p>This macro disables the HDMI TX PIO peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#adc65c495c5346d5026795fd9ae6d7cd7" title="This macro disables the HDMI TX PIO peripheral. ">XV_HdmiTx1_PioDisable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ac338e05672272398dfcd6748dd92da1a">XV_HdmiTx1_Stop()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_PioEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a7b92bd89968718f069ca23ff200f90b0">XV_HDMITX1_PIO_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a7dbedee4c4749f3d28da3b493c792cb6">XV_HDMITX1_PIO_CTRL_RUN_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a7b92bd89968718f069ca23ff200f90b0"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a7b92bd89968718f069ca23ff200f90b0">XV_HDMITX1_PIO_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_CTRL_SET_OFFSET</div><div class="ttdoc">PIO Control Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:138</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a7dbedee4c4749f3d28da3b493c792cb6"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a7dbedee4c4749f3d28da3b493c792cb6">XV_HDMITX1_PIO_CTRL_RUN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_CTRL_RUN_MASK</div><div class="ttdoc">PIO Control Run mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:186</div></div>
</div><!-- fragment -->
<p>This macro enables the HDMI TX PIO peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#aee2b7ea5870d1eb94eb90bbfe2130e50" title="This macro enables the HDMI TX PIO peripheral. ">XV_HdmiTx1_PioEnable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ac0969e712c2e4170732589e66359f592">XV_HdmiTx1_Start()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_PioIntrClear</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#aad716fe9cadcb6ad07df46c18b0f67d9">XV_HDMITX1_PIO_STA_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#ab68b9045690c17f85d3d454f182aaaa4">XV_HDMITX1_PIO_STA_IRQ_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_ab68b9045690c17f85d3d454f182aaaa4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#ab68b9045690c17f85d3d454f182aaaa4">XV_HDMITX1_PIO_STA_IRQ_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_STA_IRQ_MASK</div><div class="ttdoc">PIO Status Interrupt mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:192</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_aad716fe9cadcb6ad07df46c18b0f67d9"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#aad716fe9cadcb6ad07df46c18b0f67d9">XV_HDMITX1_PIO_STA_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_STA_OFFSET</div><div class="ttdoc">PIO Status Register * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:144</div></div>
</div><!-- fragment -->
<p>This macro clears HDMI TX PIO interrupt. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a7e5757f2158d4aae374aa076fbc147e7" title="This macro clears HDMI TX PIO interrupt. ">XV_HdmiTx1_PioIntrClear(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_PioIntrDisable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#ab2c8c843f94dae2bf7b7050da886ee8f">XV_HDMITX1_PIO_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a633284b6032afb987ebdc09d68e111a5">XV_HDMITX1_PIO_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_ab2c8c843f94dae2bf7b7050da886ee8f"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#ab2c8c843f94dae2bf7b7050da886ee8f">XV_HDMITX1_PIO_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_CTRL_CLR_OFFSET</div><div class="ttdoc">PIO Control Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:141</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a633284b6032afb987ebdc09d68e111a5"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a633284b6032afb987ebdc09d68e111a5">XV_HDMITX1_PIO_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_CTRL_IE_MASK</div><div class="ttdoc">PIO Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:187</div></div>
</div><!-- fragment -->
<p>This macro disables interrupt in the HDMI TX PIO peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a8acc56c70efc79834e9411b6cff105c5" title="This macro disables interrupt in the HDMI TX PIO peripheral. ">XV_HdmiTx1_PioIntrDisable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, <a class="el" href="xv__hdmitx1_8h.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ac338e05672272398dfcd6748dd92da1a">XV_HdmiTx1_Stop()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_PioIntrEnable</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a7b92bd89968718f069ca23ff200f90b0">XV_HDMITX1_PIO_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a633284b6032afb987ebdc09d68e111a5">XV_HDMITX1_PIO_CTRL_IE_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a7b92bd89968718f069ca23ff200f90b0"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a7b92bd89968718f069ca23ff200f90b0">XV_HDMITX1_PIO_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_CTRL_SET_OFFSET</div><div class="ttdoc">PIO Control Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:138</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a633284b6032afb987ebdc09d68e111a5"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a633284b6032afb987ebdc09d68e111a5">XV_HDMITX1_PIO_CTRL_IE_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_CTRL_IE_MASK</div><div class="ttdoc">PIO Control Interrupt Enable mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:187</div></div>
</div><!-- fragment -->
<p>This macro enables interrupt in the HDMI TX PIO peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#ac1422deaecdcaa680769832bbcfaf8a7" title="This macro enables interrupt in the HDMI TX PIO peripheral. ">XV_HdmiTx1_PioIntrEnable(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, <a class="el" href="xv__hdmitx1_8h.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ac0969e712c2e4170732589e66359f592">XV_HdmiTx1_Start()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_Reset</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Reset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (Reset) { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a01feb7322f445f662f190d24c4d82583">XV_HDMITX1_PIO_OUT_RST_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a01feb7322f445f662f190d24c4d82583">XV_HDMITX1_PIO_OUT_RST_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a34819a1c42353de5eec449bc38c93efc"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_CLR_OFFSET</div><div class="ttdoc">PIO Out Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:153</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a01feb7322f445f662f190d24c4d82583"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a01feb7322f445f662f190d24c4d82583">XV_HDMITX1_PIO_OUT_RST_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_RST_MASK</div><div class="ttdoc">PIO Out Reset mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:196</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a916d49f0a22d9ef6e369ff80353e00af"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_SET_OFFSET</div><div class="ttdoc">PIO Out Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:150</div></div>
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<p>This macro asserts or releases the HDMI TX reset. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">Reset</td><td>specifies TRUE/FALSE value to either assert or release HDMI TX reset.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI . Therefore, clearing the PIO reset output will assert the HDMI link and video reset. C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a472ba57070bc4e736991f19f06490680" title="This macro asserts or releases the HDMI TX reset. ">XV_HdmiTx1_Reset(XV_HdmiTx1 *InstancePtr, u8 Reset)</a> </dd></dl>

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          <td class="memname">#define XV_HdmiTx1_SetMode</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a>), \</div>
<div class="line">                            (<a class="code" href="xv__hdmitx1__hw_8h.html#a4ce35ba56d898dd0b26cc1466d7ff9e6">XV_HDMITX1_PIO_OUT_MODE_MASK</a>))</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a4ce35ba56d898dd0b26cc1466d7ff9e6"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a4ce35ba56d898dd0b26cc1466d7ff9e6">XV_HDMITX1_PIO_OUT_MODE_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_MODE_MASK</div><div class="ttdoc">PIO Out Mode mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:197</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a916d49f0a22d9ef6e369ff80353e00af"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_SET_OFFSET</div><div class="ttdoc">PIO Out Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:150</div></div>
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<p>This macro sets the mode bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#af3a6c361d3eb8f9bc43cc1d4f6bc2269" title="This macro sets the mode bit. ">XV_HdmiTx1_SetMode(XV_HdmiTx1 *InstancePtr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#aa350caac92add60e1c85f257dbf88bdd">XV_HdmiTx1_SetHdmiFrlMode()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a214597c0aaa431427bb76ec6948563b8">XV_HdmiTx1_SetHdmiTmdsMode()</a>.</p>

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          <td class="memname">#define XV_HdmiTx1_SetScrambler</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (SetClr) { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#aa6ac2799e1faa5133f3ab35018aba54d">XV_HDMITX1_PIO_OUT_SCRM_MASK</a>)); \</div>
<div class="line">                (InstancePtr)-&gt;Stream.IsScrambled = (TRUE); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#aa6ac2799e1faa5133f3ab35018aba54d">XV_HDMITX1_PIO_OUT_SCRM_MASK</a>)); \</div>
<div class="line">                (InstancePtr)-&gt;Stream.IsScrambled = (FALSE); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a34819a1c42353de5eec449bc38c93efc"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_CLR_OFFSET</div><div class="ttdoc">PIO Out Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:153</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_aa6ac2799e1faa5133f3ab35018aba54d"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#aa6ac2799e1faa5133f3ab35018aba54d">XV_HDMITX1_PIO_OUT_SCRM_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_SCRM_MASK</div><div class="ttdoc">PIO Out Scrambler mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:210</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a916d49f0a22d9ef6e369ff80353e00af"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_PIO_OUT_SET_OFFSET</div><div class="ttdoc">PIO Out Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:150</div></div>
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<p>This macro controls the HDMI TX Scrambler. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either set ON or clear Scrambler.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a669f967b9baf869d60aa8dc35297ee3a" title="This macro controls the HDMI TX Scrambler. ">XV_HdmiTx1_SetScrambler(XV_HdmiTx1 *InstancePtr, u8 SetClr)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a83f6939b0f5205344a276489afe45223">XV_HdmiTx1_Scrambler()</a>.</p>

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<a class="anchor" id="ae2f8cf0015a6f22105b8e63f0388ff28"></a>
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          <td class="memname">#define XV_HdmiTx1_VrrControl</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InstancePtr, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">SetClr&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">{ \</div>
<div class="line">        if (SetClr) { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a09460db96023dedd0a3baf757e53447a">XV_HDMITX1_AUX_CTRL_VRR_EN_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">        else { <a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">\</a></div>
<div class="line"><a class="code" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">		XV_HdmiTx1_WriteReg</a>((InstancePtr)-&gt;Config.BaseAddress, \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a>), \</div>
<div class="line">                                    (<a class="code" href="xv__hdmitx1__hw_8h.html#a09460db96023dedd0a3baf757e53447a">XV_HDMITX1_AUX_CTRL_VRR_EN_MASK</a>)); \</div>
<div class="line">        } \</div>
<div class="line">}</div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_af4ba16c8e4e0505aa1e7ea79d06eb2d4"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a></div><div class="ttdeci">#define XV_HdmiTx1_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">This macro writes a value to a HDMI TX register. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:763</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a09460db96023dedd0a3baf757e53447a"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a09460db96023dedd0a3baf757e53447a">XV_HDMITX1_AUX_CTRL_VRR_EN_MASK</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_VRR_EN_MASK</div><div class="ttdoc">AUX Control VRR En mask. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:382</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a97406fdf0b5b815f1a99e48f9f769ab9"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_SET_OFFSET</div><div class="ttdoc">AUX Control Register Set * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:357</div></div>
<div class="ttc" id="xv__hdmitx1__hw_8h_html_a93a082440892ddad44f45085a507d526"><div class="ttname"><a href="xv__hdmitx1__hw_8h.html#a93a082440892ddad44f45085a507d526">XV_HDMITX1_AUX_CTRL_CLR_OFFSET</a></div><div class="ttdeci">#define XV_HDMITX1_AUX_CTRL_CLR_OFFSET</div><div class="ttdoc">AUX Control Register Clear * offset. </div><div class="ttdef"><b>Definition:</b> xv_hdmitx1_hw.h:360</div></div>
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<p>This macro allows enabling/disabling of VRR in HDMI Tx. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">SetClr</td><td>specifies TRUE/FALSE value to either enable or disable the VFP Event</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#ae2f8cf0015a6f22105b8e63f0388ff28" title="This macro allows enabling/disabling of VRR in HDMI Tx. ">XV_HdmiTx1_VrrControl(XV_HdmiTx1 *InstancePtr, u8 SetClr)</a> </dd></dl>

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<h2 class="groupheader">Typedef Documentation</h2>
<a class="anchor" id="a5bb0fa4a27e544cf4df3fa3aad14011a"></a>
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          <td class="memname">typedef void(* XV_HdmiTx1_Callback)(void *CallbackRef)</td>
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<p>Callback type for Vsync event interrupt. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">CallbackRef</td><td>is a callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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<h2 class="groupheader">Enumeration Type Documentation</h2>
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          <td class="memname">enum <a class="el" href="xv__hdmitx1_8h.html#af9b30d0cba10a37e4719114fe400ea64">XV_HdmiTx1_HandlerType</a></td>
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<p>These constants specify different types of handler and used to differentiate interrupt requests from peripheral. </p>

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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">void XV_HdmiTx1_AudioEnable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This macro enables audio in HDMI TX core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a0b6ca194e0811b7201545d206d1a49e3">XV_HDMITX1_AUD_CTRL_RUN_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ac630a1dbb83be6d4e64757a3d09c2cc0">XV_HDMITX1_AUD_CTRL_SET_OFFSET</a>, <a class="el" href="xv__hdmitx1_8c.html#ad22b60a3d798ee469dcc71a04100843d">XV_HdmiTx1_FRLACRStart()</a>, <a class="el" href="xv__hdmitx1_8c.html#a7f1498e69d193cbd626999414e863558">XV_HdmiTx1_TMDSACRStart()</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae0d426d4100141b3e9f9d943197d07e8">XV_HdmiTx1_SetAudioChannels()</a>, <a class="el" href="xv__hdmitx1_8h.html#a23a20e6c1144064686e03fd0650ec46f">XV_HdmiTx1_SetAudioFormat()</a>, <a class="el" href="xv__hdmitx1_8h.html#aa350caac92add60e1c85f257dbf88bdd">XV_HdmiTx1_SetHdmiFrlMode()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a214597c0aaa431427bb76ec6948563b8">XV_HdmiTx1_SetHdmiTmdsMode()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_Aux_Dsc_Send_Data </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Data</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function transmits the DSC packet data. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">Data</td><td>value to be written</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___config.html#ac9448a4fb60f4bf571da4e1c49bf0056">XV_HdmiTx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiTx1_Aux_Dsc_Send_Header </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Data</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function transmits the DSC packet header. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">Data</td><td>value to be written</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___config.html#ac9448a4fb60f4bf571da4e1c49bf0056">XV_HdmiTx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiTx1_AuxEnable </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function enables the HDMI TX Auxiliary (AUX) peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#add021f22d0ef7e0de595b74f105d4572">XV_HDMITX1_AUX_CTRL_RUN_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a97406fdf0b5b815f1a99e48f9f769ab9">XV_HDMITX1_AUX_CTRL_SET_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a86472ba3e4497749a3b0af4fd446137d">XV_HdmiTx1_FrlStreamStart()</a>, <a class="el" href="xv__hdmitx1_8h.html#aa350caac92add60e1c85f257dbf88bdd">XV_HdmiTx1_SetHdmiFrlMode()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a214597c0aaa431427bb76ec6948563b8">XV_HdmiTx1_SetHdmiTmdsMode()</a>.</p>

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          <td class="memname">u32 XV_HdmiTx1_AuxSend </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function transmits the infoframes generated by the processor. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if infoframes transmitted successfully.</li>
<li>XST_FAILURE if AUX FIFO is full.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1.html#a2fcf639e71cb04c30a8f00c3ce401f63">XV_HdmiTx1::Aux</a>, <a class="el" href="struct_x_v___hdmi_tx1___config.html#ac9448a4fb60f4bf571da4e1c49bf0056">XV_HdmiTx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ae77c642360ad975ab150de8a8c269d25">XV_HDMITX1_AUX_DAT_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a7bfb37aac0d6dd176a5d5be6e05697d9">XV_HDMITX1_AUX_STA_FIFO_FUL_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a14dcc9b57dc6ff4a5d43c9df86e54723">XV_HDMITX1_AUX_STA_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a778b10c4ff90127e6787100a6836a791">XV_HDMITX1_AUX_STA_PKT_RDY_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">int XV_HdmiTx1_CfgInitialize </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1___config.html">XV_HdmiTx1_Config</a> *&#160;</td>
          <td class="paramname"><em>CfgPtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">UINTPTR&#160;</td>
          <td class="paramname"><em>EffectiveAddr</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function initializes the HDMI TX core. </p>
<p>This function must be called prior to using the HDMI TX core. Initialization of the HDMI TX includes setting up the instance data and ensuring the hardware is in a quiescent state.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">CfgPtr</td><td>points to the configuration structure associated with the HDMI TX core. </td></tr>
    <tr><td class="paramname">EffectiveAddr</td><td>is the base address of the device. If address translation is being used, then this parameter must reflect the virtual base address. Otherwise, the physical address should be used.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if XV_HdmiTx1_CfgInitialize was successful.</li>
<li>XST_FAILURE if HDMI TX PIO ID mismatched.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#ac110c3e0296b6f95e3647410e3ddadd2">XV_HdmiTx1_Stream::Audio</a>, <a class="el" href="struct_x_v___hdmi_tx1___config.html#ac9448a4fb60f4bf571da4e1c49bf0056">XV_HdmiTx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#aef6b3f6753d278df67f1c9803f667e08">XV_HdmiTx1::ConnectCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a7fa66e3baa8894a6c59b3fbc96d18354">XV_HdmiTx1_Stream::CorePixPerClk</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a2b619bbff33578107cf420cacecd2e18">XV_HdmiTx1::DscDecodeFailCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#aa75eb56d2fcf4058da44bb2a2c3eba9b">XV_HdmiTx1::DynHdrMtwCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#aeb7e0c79ea8b44c2eac37ce9a063587e">XV_HdmiTx1_Stream::Frl</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#ac495d5b8980b11427969918c7ea6eb56">XV_HdmiTx1::FrlConfigCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#ada61680a6092bdfeb4057cbd70e07584">XV_HdmiTx1::FrlFfeCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a4a76a4f44c11da6514bfcd2b366ee79a">XV_HdmiTx1::FrlStartCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#abc1b2a59bc184f8461952572773a3b1d">XV_HdmiTx1::FrlStopCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#afa7e042159e99edf7f02139af8cba046">XV_HdmiTx1_Stream::IsConnected</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#abc4e2c7cd581d8e407d845f1a620d3d8">XV_HdmiTx1::IsReady</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#ac95410542d1d4eed581f66c49e70a9bb">XV_HdmiTx1_Frl::Lanes</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#a7ae9e5018c441354a23323082dc6aa76">XV_HdmiTx1_Frl::MaxFrlRate</a>, <a class="el" href="struct_x_v___hdmi_tx1___config.html#a7f80ad7a8e8dd3c68792fcda5196f74a">XV_HdmiTx1_Config::MaxFrlRate</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a9947243bcf378409927347939617a886">XV_HdmiTx1_Stream::OverrideScrambler</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#ade3e232e0d44b497785c50202a441ef6">XV_HdmiTx1_Frl::RateLock</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a59d80fb969eedd5ca7c59960fe5460a7">XV_HdmiTx1_Stream::State</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a4929690dcb3684990ea7cb5d2f6cb497">XV_HdmiTx1::StreamDownCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a01870b62d198af5f708b320a2339f9d3">XV_HdmiTx1::StreamUpCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a7be7f63d8a5bd9f54b4e186dc82820bc">XV_HdmiTx1::TmdsConfigCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#af48a03329a29f3358af6bc289f510797">XV_HdmiTx1::ToggleCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#afb1cf1b7d51092ef7429b95a4353ab4d">XV_HdmiTx1_Frl::TrainingState</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a529cf861436423034baa776592647e3e">XV_HdmiTx1::VsCallback</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a279874e2cee1de19fee34f5f25fe4198">XV_HDMITX1_AUD_CTRL_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ac630a1dbb83be6d4e64757a3d09c2cc0">XV_HDMITX1_AUD_CTRL_SET_OFFSET</a>, <a class="el" href="xv__hdmitx1_8h.html#ac80822fe192ddd125e321cdf4c9d4608">XV_HdmiTx1_AudioDisable</a>, <a class="el" href="xv__hdmitx1_8h.html#a885cea7ad25eb7470e839cbe329b8ec4">XV_HdmiTx1_AuxDisable</a>, <a class="el" href="xv__hdmitx1_8c.html#a626c53ccaef2fea0d712d363e80691ac">XV_HdmiTx1_Clear()</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a5f8f27b07f3e43e7bf04c5bda2e1179f">XV_HDMITX1_CONNECT_CONF_OFFSET</a>, <a class="el" href="xv__hdmitx1_8h.html#a48c24836f4ff579b8bf3ed1dfc298747">XV_HdmiTx1_DdcDisable</a>, <a class="el" href="xv__hdmitx1_8h.html#a1a4bb321f73f08e71204821bb3c68b3d">XV_HdmiTx1_DdcIntrClear</a>, <a class="el" href="xv__hdmitx1_8h.html#a8f3afde27c63f277de13d600ae3118ef">XV_HdmiTx1_FrlExecute()</a>, <a class="el" href="xv__hdmitx1_8h.html#a8c3339f7859efd76ec6a3ee262e20caa">XV_HdmiTx1_FrlExtVidCkeSource()</a>, <a class="el" href="xv__hdmitx1__frl_8h.html#a58012592af0eafb0b1bdbce08aa70169">XV_HdmiTx1_FrlIntrDisable</a>, <a class="el" href="xv__hdmitx1__frl_8h.html#aaa2b17ec29b80b19f9fa18abadeef78b">XV_HdmiTx1_FrlIntrEnable</a>, <a class="el" href="xv__hdmitx1_8h.html#a9ae3d651a0d9b2258415a0fcd243ee0c">XV_HdmiTx1_FrlReset()</a>, <a class="el" href="xv__hdmitx1_8h.html#ab4c65e1485f6003c182e86c2423d1934">XV_HdmiTx1_GetTime1Ms</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a8239e53495feea5050dbda9cad646119">XV_HDMITX1_HPD_TIMEGRID_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a02751a20bad34eb921ded41ecd6449bd">XV_HDMITX1_MASK_16</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a85275d4df3edf2c08d38d544b5928c95">XV_HDMITX1_PIO_ID</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a771c245a4146fa673670d145a49ab42c">XV_HDMITX1_PIO_ID_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a47d0be5976cb417367f227882aba616a">XV_HDMITX1_PIO_IN_BRDG_LOCKED_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ad7989878b63e6d1ccc17b9fffebdb1e7">XV_HDMITX1_PIO_IN_BRDG_OVERFLOW_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a9d53bbc6e4513d332030da84a4d5366c">XV_HDMITX1_PIO_IN_BRDG_UNDERFLOW_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a0840f8be0f908f0ebf7f88da62919041">XV_HDMITX1_PIO_IN_EVT_FE_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a083e42899636cd5e11e57dc81ed473d1">XV_HDMITX1_PIO_IN_EVT_RE_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a8e4ab9f93df19e5011f0abc4b62d6d68">XV_HDMITX1_PIO_IN_HPD_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#acaa33be8f32fd160bc231fe83d8e4e7b">XV_HDMITX1_PIO_IN_HPD_TOGGLE_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a9c67bb4f654071b9bbd7c0bb57bd431b">XV_HDMITX1_PIO_IN_LNK_RDY_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#aa69dc4de1fcc61075bb66a5f72498f09">XV_HDMITX1_PIO_IN_VS_MASK</a>, <a class="el" href="xv__hdmitx1_8h.html#adc65c495c5346d5026795fd9ae6d7cd7">XV_HdmiTx1_PioDisable</a>, <a class="el" href="xv__hdmitx1_8h.html#a7e5757f2158d4aae374aa076fbc147e7">XV_HdmiTx1_PioIntrClear</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>, <a class="el" href="xv__hdmitx1_8c.html#a214597c0aaa431427bb76ec6948563b8">XV_HdmiTx1_SetHdmiTmdsMode()</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a52b7d366cc179f1aa90b20ae9ed5a6de">XV_HDMITX1_SHIFT_16</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a3154f6e901d66ba2320ccf5ab4d08821">XV_HDMITX1_TOGGLE_CONF_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiTx1_Clear </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function clear the HDMI TX variables and sets it to the defaults. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>This is required after a reset or init. </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_ClearFrlWrongLtp </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function clears the debugging flag which would have prevented the core from sending out correct LTP. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#aeb7e0c79ea8b44c2eac37ce9a063587e">XV_HdmiTx1_Stream::Frl</a>, and <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>.</p>

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          <td class="memname">void XV_HdmiTx1_ClearGcpAvmuteBit </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function clears the HDMI TX AUX GCP register AVMUTE bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#acdf644126236c17fe0561f8b7b35e848">XV_HDMITX1_PIO_OUT_GCP_AVMUTE_MASK</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiTx1_ClearGcpClearAvmuteBit </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function clears the HDMI TX AUX GCP register CLEAR_AVMUTE bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#af12c5bc4580008e386420488c4dc2945">XV_HDMITX1_PIO_OUT_GCP_CLEARAVMUTE_MASK</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">int XV_HdmiTx1_ClockRatio </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function controls the TMDS clock ratio. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if HDMI 2.0</li>
<li>XST_FAILURE if HDMI 1.4</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a4cee4a4b0708d7e886ab923114753d75">XV_HdmiTx1_Stream::ScdcSupport</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#abd62e567ccef9f34c2614909fed625ce">XV_HdmiTx1_Stream::TMDSClockRatio</a>, <a class="el" href="xv__hdmitx1_8c.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, and <a class="el" href="xv__hdmitx1_8c.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a7a20221c997a381a61b4e7e98c5a4370">XV_HdmiTx1_SetStream()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_DdcInit </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Frequency</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function prepares TX DDC peripheral to use. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">Frequency</td><td>specifies the value that needs to be set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___config.html#ac9448a4fb60f4bf571da4e1c49bf0056">XV_HdmiTx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ac2f786b3061b4df4c53544b6e90f9644">XV_HDMITX1_DDC_CTRL_CLK_DIV_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a446a4adab4ed3b06eb0834191bfa15d9">XV_HDMITX1_DDC_CTRL_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a6c007b416e2eeb72cc040a16b285b57c">XV_HdmiTx1_SetAxiClkFreq()</a>.</p>

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          <td class="memname">int XV_HdmiTx1_DdcRead </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Slave</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>Length</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Buffer</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Stop</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function reads data from DDC peripheral from given slave address. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">Slave</td><td>specifies the slave address from where data needs to be read. </td></tr>
    <tr><td class="paramname">Length</td><td>specifies number of bytes to be read. </td></tr>
    <tr><td class="paramname">Buffer</td><td>specifies a pointer to u8 variable that will be filled with data. </td></tr>
    <tr><td class="paramname">Stop</td><td>specifies the stop flag which is either TRUE/FALSE.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if an acknowledgement received and timeout.</li>
<li>XST_FAILURE if no acknowledgement received.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a7c6cd9c2d19d95db83b737e22375377a">XV_HDMITX1_DDC_CMD_RD_TOKEN</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ac055e0da09799cd2bf1deaaf7d594a9b">XV_HDMITX1_DDC_CMD_STP_TOKEN</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a845b5618c93a1561f1a0a14c8f3eff8e">XV_HDMITX1_DDC_CMD_STR_TOKEN</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a138fe51f7ce3717cfaf38b3a67098566">XV_HDMITX1_DDC_CMD_WR_TOKEN</a>, <a class="el" href="xv__hdmitx1_8h.html#a48c24836f4ff579b8bf3ed1dfc298747">XV_HdmiTx1_DdcDisable</a>, <a class="el" href="xv__hdmitx1_8h.html#aa2bd58dc021ee4fe7b52eca1125f39b6">XV_HdmiTx1_DdcEnable</a>, <a class="el" href="xv__hdmitx1_8c.html#a76353bf20bfbb1f162c56117c2f71b59">XV_HdmiTx1_DdcGetAck()</a>, <a class="el" href="xv__hdmitx1_8h.html#a0a0262addeb5640e4b2d681202559056">XV_HdmiTx1_DdcIntrDisable</a>, <a class="el" href="xv__hdmitx1_8c.html#a0320f379245cb86d83f5eb565adf6ad8">XV_HdmiTx1_DdcReadData()</a>, <a class="el" href="xv__hdmitx1_8c.html#a12496535333a1068fef5929b566faf5a">XV_HdmiTx1_DdcWaitForDone()</a>, <a class="el" href="xv__hdmitx1_8c.html#a199e2e62f3ebaa5993d935bf2bde0462">XV_HdmiTx1_DdcWriteCommand()</a>, <a class="el" href="xv__hdmitx1_8h.html#abe9d06ce9943cedc448f905806cbc6a2">XV_HdmiTx1_GetFrlTimer()</a>, <a class="el" href="xv__hdmitx1_8h.html#a8acc56c70efc79834e9411b6cff105c5">XV_HdmiTx1_PioIntrDisable</a>, <a class="el" href="xv__hdmitx1_8h.html#ac1422deaecdcaa680769832bbcfaf8a7">XV_HdmiTx1_PioIntrEnable</a>, and <a class="el" href="xv__hdmitx1_8h.html#a5c81c3da135fd69e74aa106dadce0ca4">XV_HdmiTx1_SetFrlTimerClockCycles()</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#af8b34671e3735035e8dd68f6bdbb7904">XV_HdmiTx1_ClockRatio()</a>, <a class="el" href="xv__hdmitx1_8h.html#a9a71a92b44c225aa265a3c5852971df7">XV_HdmiTx1_DdcReadReg()</a>, <a class="el" href="xv__hdmitx1_8h.html#ab9b6a97a3396e177e52f69f6b5d88123">XV_HdmiTx1_DdcWriteField()</a>, <a class="el" href="xv__hdmitx1_8h.html#a83f6939b0f5205344a276489afe45223">XV_HdmiTx1_Scrambler()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a74ffa1683c6444f4ba05916b5c15312a">XV_HdmiTx1_ShowSCDC()</a>.</p>

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          <td class="memname">int XV_HdmiTx1_DdcReadReg </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Slave</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>Length</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>RegAddr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Buffer</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function reads specified register from DDC peripheral from given slave address. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">Slave</td><td>specifies the slave address from where data needs to be read. </td></tr>
    <tr><td class="paramname">Length</td><td>specifies number of bytes to be read. </td></tr>
    <tr><td class="paramname">RegAddr</td><td>specifies the register address from where data needs to be read. </td></tr>
    <tr><td class="paramname">Buffer</td><td>specifies a pointer to u8 variable that will be filled with data. </td></tr>
    <tr><td class="paramname">Stop</td><td>specifies the stop flag which is either TRUE/FALSE.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if an acknowledgement received and timeout.</li>
<li>XST_FAILURE if no acknowledgement received.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1_8c.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, and <a class="el" href="xv__hdmitx1_8c.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a4623f1c32afecde613bfb2c4517597b1">XV_HdmiTx1_GetScdcEdRegisters()</a>.</p>

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          <td class="memname">int XV_HdmiTx1_DdcWrite </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Slave</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>Length</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Buffer</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Stop</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function writes data from DDC peripheral from given slave address. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">Slave</td><td>specifies the slave address from where data needs to be read. </td></tr>
    <tr><td class="paramname">Length</td><td>specifies number of bytes to be read. </td></tr>
    <tr><td class="paramname">Buffer</td><td>specifies a pointer to u8 variable that will be filled with data. </td></tr>
    <tr><td class="paramname">Stop</td><td>specifies the stop flag which is either TRUE/FALSE.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if an acknowledgement received and timeout.</li>
<li>XST_FAILURE if no acknowledgement received.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#ac055e0da09799cd2bf1deaaf7d594a9b">XV_HDMITX1_DDC_CMD_STP_TOKEN</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a845b5618c93a1561f1a0a14c8f3eff8e">XV_HDMITX1_DDC_CMD_STR_TOKEN</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a138fe51f7ce3717cfaf38b3a67098566">XV_HDMITX1_DDC_CMD_WR_TOKEN</a>, <a class="el" href="xv__hdmitx1_8h.html#a48c24836f4ff579b8bf3ed1dfc298747">XV_HdmiTx1_DdcDisable</a>, <a class="el" href="xv__hdmitx1_8h.html#aa2bd58dc021ee4fe7b52eca1125f39b6">XV_HdmiTx1_DdcEnable</a>, <a class="el" href="xv__hdmitx1_8c.html#a76353bf20bfbb1f162c56117c2f71b59">XV_HdmiTx1_DdcGetAck()</a>, <a class="el" href="xv__hdmitx1_8h.html#a0a0262addeb5640e4b2d681202559056">XV_HdmiTx1_DdcIntrDisable</a>, <a class="el" href="xv__hdmitx1_8c.html#a12496535333a1068fef5929b566faf5a">XV_HdmiTx1_DdcWaitForDone()</a>, <a class="el" href="xv__hdmitx1_8c.html#a199e2e62f3ebaa5993d935bf2bde0462">XV_HdmiTx1_DdcWriteCommand()</a>, <a class="el" href="xv__hdmitx1_8h.html#abe9d06ce9943cedc448f905806cbc6a2">XV_HdmiTx1_GetFrlTimer()</a>, <a class="el" href="xv__hdmitx1_8h.html#a8acc56c70efc79834e9411b6cff105c5">XV_HdmiTx1_PioIntrDisable</a>, <a class="el" href="xv__hdmitx1_8h.html#ac1422deaecdcaa680769832bbcfaf8a7">XV_HdmiTx1_PioIntrEnable</a>, and <a class="el" href="xv__hdmitx1_8h.html#a5c81c3da135fd69e74aa106dadce0ca4">XV_HdmiTx1_SetFrlTimerClockCycles()</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#af8b34671e3735035e8dd68f6bdbb7904">XV_HdmiTx1_ClockRatio()</a>, <a class="el" href="xv__hdmitx1_8h.html#a9a71a92b44c225aa265a3c5852971df7">XV_HdmiTx1_DdcReadReg()</a>, <a class="el" href="xv__hdmitx1_8h.html#ab9b6a97a3396e177e52f69f6b5d88123">XV_HdmiTx1_DdcWriteField()</a>, <a class="el" href="xv__hdmitx1_8h.html#ab2deec246bd2a50733347cdb293e7d59">XV_HdmiTx1_DetectHdmi20()</a>, <a class="el" href="xv__hdmitx1_8h.html#a83f6939b0f5205344a276489afe45223">XV_HdmiTx1_Scrambler()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a74ffa1683c6444f4ba05916b5c15312a">XV_HdmiTx1_ShowSCDC()</a>.</p>

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          <td class="memname">int XV_HdmiTx1_DdcWriteField </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XV_HdmiTx1_ScdcFieldType&#160;</td>
          <td class="paramname"><em>Field</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Value</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function writes the specified SCDC Field. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
    <tr><td class="paramname">Field</td><td>specifies the fields from SCDC channels to be written</td></tr>
    <tr><td class="paramname">Value</td><td>specifies the values to be written</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS</li>
<li>XST_FAILURE</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___scdc_field.html#a39181b894a165c980e854e870fb00880">XV_HdmiTx1_ScdcField::Mask</a>, <a class="el" href="struct_x_v___hdmi_tx1___scdc_field.html#a97c8c91664f438732ef2c372f99aefbb">XV_HdmiTx1_ScdcField::Offset</a>, <a class="el" href="struct_x_v___hdmi_tx1___scdc_field.html#ac7ec60c1297e56cef90f46f30078f81c">XV_HdmiTx1_ScdcField::Shift</a>, <a class="el" href="xv__hdmitx1_8c.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, and <a class="el" href="xv__hdmitx1_8c.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ad03f1110009425d476e007abd30898d6">XV_HdmiTx1_FrlRate()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a730bc782f3ed005fbff8e45c1dbd055a">XV_HdmiTx1_FrlTrainingInit()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_DebugInfo </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function prints debug information on STDIO/UART console. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___config.html#ac9448a4fb60f4bf571da4e1c49bf0056">XV_HdmiTx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#afb2c02dfd40e7248cb5137d1fda16451">XV_HDMITX1_ANLZ_HBP_HS_HPB_SZ_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a0b0c1fc1bd8023ff5443e48be1a37d52">XV_HDMITX1_ANLZ_HBP_HS_HPB_SZ_SHIFT</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a2a337b11e7ed5c655aaa779fcb92238e">XV_HDMITX1_ANLZ_HBP_HS_HS_SZ_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a1e0129ded92751eb5637c0d3a3af7ec7">XV_HDMITX1_ANLZ_HBP_HS_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ab5ee2d3c0b53adc5e1baabe4bc0d8471">XV_HDMITX1_ANLZ_LN_ACT_ACT_SZ_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a553fc17abc52bfc2212f49243b910963">XV_HDMITX1_ANLZ_LN_ACT_LN_SZ_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#aecc45e839afee440ecd5c614a0f6c379">XV_HDMITX1_ANLZ_LN_ACT_LN_SZ_SHIFT</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ad97a50cec14720080dc2ff6e5fd41809">XV_HDMITX1_ANLZ_LN_ACT_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a4839aca0ca1a11f8b1553026a33d8e6e">XV_HDMITX1_DBG_STS_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a5fe062b0a3114ac13ab10e99fd02dcd3">XV_HDMITX1_FRL_CTRL_LN_OP_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#abc06f99f814e758f194f5afab57fd7e1">XV_HDMITX1_FRL_CTRL_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#af14a628baf787a604f23d2114b5ef16a">XV_HDMITX1_FRL_CTRL_OP_MODE_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#abcfb2ad0c96c0240bd2211dba81810d0">XV_HDMITX1_FRL_LNK_CLK_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ab380ac5aacd7ffc41be4c522f4a86b76">XV_HDMITX1_FRL_STA_LNK_CLK_OOS_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#af69097b14c333e4e03d8934c68e5666a">XV_HDMITX1_FRL_STA_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ab43b8614d7ac425f46252b52f4934fe5">XV_HDMITX1_FRL_VCKE_EXT_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ae77246dd4776e8a41f7b92c093c4e1a0">XV_HDMITX1_FRL_VID_CLK_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a47d0be5976cb417367f227882aba616a">XV_HDMITX1_PIO_IN_BRDG_LOCKED_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ab20b6e84abcd0378fbc8e17282eacb16">XV_HDMITX1_PIO_IN_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a4ce35ba56d898dd0b26cc1466d7ff9e6">XV_HDMITX1_PIO_OUT_MODE_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#aef14faec6d7dec76359597de87c027e1">XV_HDMITX1_PIO_OUT_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a2a61ed968e178ed839d00ed19855ded3">XV_HDMITX1_VCKE_SYS_CNT_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#acdb9781981b55f2a70cf2ef4e50e00cb">XV_HDMITX1_VER_ID_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#ab85b13706cb38b267c66b44d3533e000">XV_HDMITX1_VER_VERSION_OFFSET</a>.</p>

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          <td class="memname">int XV_HdmiTx1_DetectHdmi20 </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function detects connected sink is a HDMI 2.0/HDMI 1.4 sink device and sets appropriate flag in the TX stream. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if HDMI 2.0</li>
<li>XST_FAILURE if HDMI 1.4</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a4cee4a4b0708d7e886ab923114753d75">XV_HdmiTx1_Stream::ScdcSupport</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, and <a class="el" href="xv__hdmitx1_8c.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>.</p>

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          <td class="memname">int XV_HdmiTx1_ExecFrlState </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function executes the different of states of FRL. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#aeb7e0c79ea8b44c2eac37ce9a063587e">XV_HdmiTx1_Stream::Frl</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, and <a class="el" href="struct_x_v___hdmi_tx1___frl.html#afb1cf1b7d51092ef7429b95a4353ab4d">XV_HdmiTx1_Frl::TrainingState</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a76d80c3b0078c28a7e0672a581588ea4">XV_HdmiTx1_StartFrlTraining()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_EXT_SYSRST </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Reset</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function asserts or releases the HDMI TX External SYSRST. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">Reset</td><td>specifies TRUE/FALSE value to either assert or release HDMI TX External SYSRST.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI TX. Therefore, clearing the PIO reset output will assert the HDMI External system reset. C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a74e6c88c1599a6f0290c5db420bc8d50" title="This function asserts or releases the HDMI TX External SYSRST. ">XV_HdmiTx1_EXT_SYSRST(XV_HdmiTx1 *InstancePtr, u8 Reset)</a> </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a11a55e987433d85234ed12bbaeae13ad">XV_HDMITX1_PIO_OUT_EXT_SYSRST_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiTx1_EXT_VRST </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Reset</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function asserts or releases the HDMI TX External VRST. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">Reset</td><td>specifies TRUE/FALSE value to either assert or release HDMI TX External VRST.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI TX. Therefore, clearing the PIO reset output will assert the HDMI external video reset. C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#a73e17f2ac248affe52270168283ba45f" title="This function asserts or releases the HDMI TX External VRST. ">XV_HdmiTx1_EXT_VRST(XV_HdmiTx1 *InstancePtr, u8 Reset)</a> </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a0ef4633d186e31591484e815f99ef471">XV_HDMITX1_PIO_OUT_EXT_VRST_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiTx1_FRLACRStart </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function Starts the internal ACR module for FRL. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Active audio format of HDMI Tx</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#ac110c3e0296b6f95e3647410e3ddadd2">XV_HdmiTx1_Stream::Audio</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#aeb7e0c79ea8b44c2eac37ce9a063587e">XV_HdmiTx1_Stream::Frl</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#a8d9f5de0ab29699e3308bbcd372d7888">XV_HdmiTx1_Frl::LineRate</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a07578cb7628cd825336759685d553253">XV_HDMITX1_AUD_ACR_N_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a279874e2cee1de19fee34f5f25fe4198">XV_HDMITX1_AUD_CTRL_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ac630a1dbb83be6d4e64757a3d09c2cc0">XV_HDMITX1_AUD_CTRL_SET_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae842f2e11b05dbc07382f202bffbf7ea">XV_HdmiTx1_AudioEnable()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_FrlExecute </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function executes the FRL register updates. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a6e9c4eff210d0862e3e7ca94bf7fa0e6">XV_HDMITX1_FRL_CTRL_EXEC_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ae76270b448224670d8cd9615dbac2091">XV_HDMITX1_FRL_CTRL_SET_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_FrlExtVidCkeSource </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Value</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets the source of the video clock enable. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
    <tr><td class="paramname">Value</td><td>specifies the number of FRL lanes in operation.<ul>
<li>FALSE = Internally generated video cke</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<ul>
<li>TRUE = External video cke</li>
</ul>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#aa5da06390a2ac2dc17a7581c3cc7f81a">XV_HDMITX1_FRL_CTRL_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ae76270b448224670d8cd9615dbac2091">XV_HDMITX1_FRL_CTRL_SET_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ab43b8614d7ac425f46252b52f4934fe5">XV_HDMITX1_FRL_VCKE_EXT_MASK</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_FrlModeEn </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Enable</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets the FRL operation mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
    <tr><td class="paramname">Enable</td><td>specifies the FRL mode.<ul>
<li>FALSE = TMDS</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<ul>
<li>TRUE = FRL</li>
</ul>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#aa5da06390a2ac2dc17a7581c3cc7f81a">XV_HDMITX1_FRL_CTRL_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#af14a628baf787a604f23d2114b5ef16a">XV_HDMITX1_FRL_CTRL_OP_MODE_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ae76270b448224670d8cd9615dbac2091">XV_HDMITX1_FRL_CTRL_SET_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a730bc782f3ed005fbff8e45c1dbd055a">XV_HdmiTx1_FrlTrainingInit()</a>.</p>

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          <td class="memname">int XV_HdmiTx1_FrlRate </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>FrlRate</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets the TX core's FRL Rate and sends encoded FRL_Rate data and FFE Levels to the sink through SCDC. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
    <tr><td class="paramname">MaxFrlRate</td><td>specifies maximum rates supported<ul>
<li>0 = FRL Not Supported</li>
<li>1 = 3 Lanes 3Gbps</li>
<li>2 = 4 Lanes 3Gbps</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<ul>
<li>3 = 4 Lanes 6Gbsp</li>
<li>4 = 4 Lanes 8Gbps</li>
<li>5 = 4 Lanes 10Gbps</li>
<li>6 = 4 Lanes 12Gbps</li>
</ul>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___frl.html#a82aaff9d01746d97469ad13be6c4bfb1">XV_HdmiTx1_Frl::FfeLevels</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#aeb7e0c79ea8b44c2eac37ce9a063587e">XV_HdmiTx1_Stream::Frl</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#adfeeedbdb9a0a9c4a7ecc2d7b21f3704">XV_HdmiTx1_Frl::FrlRate</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#ac95410542d1d4eed581f66c49e70a9bb">XV_HdmiTx1_Frl::Lanes</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#a8d9f5de0ab29699e3308bbcd372d7888">XV_HdmiTx1_Frl::LineRate</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a4cee4a4b0708d7e886ab923114753d75">XV_HdmiTx1_Stream::ScdcSupport</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="xv__hdmitx1_8c.html#ab9b6a97a3396e177e52f69f6b5d88123">XV_HdmiTx1_DdcWriteField()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a36c5a2a45c4aabd06c2e7fbdf26bb991">XV_HdmiTx1_SetFrlLanes()</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a730bc782f3ed005fbff8e45c1dbd055a">XV_HdmiTx1_FrlTrainingInit()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_FrlReset </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Reset</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function resets the FRL peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
    <tr><td class="paramname">Reset</td><td>specifies if the FRL peripheral is under reset or not.<ul>
<li>0 = Reset released</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<ul>
<li>1 = Reset asserted</li>
</ul>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#aa5da06390a2ac2dc17a7581c3cc7f81a">XV_HDMITX1_FRL_CTRL_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#af0adeaa6e6dbbf9da1aa465dbe5801c8">XV_HDMITX1_FRL_CTRL_RSTN_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ae76270b448224670d8cd9615dbac2091">XV_HDMITX1_FRL_CTRL_SET_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

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          <td class="memname">int XV_HdmiTx1_FrlStreamStart </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function starts FRL video stream. </p>
<p>This should be called after the bridge, video, audio are all active.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a59d80fb969eedd5ca7c59960fe5460a7">XV_HdmiTx1_Stream::State</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a01870b62d198af5f708b320a2339f9d3">XV_HdmiTx1::StreamUpCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#ac371f98870269cb29be2e43d48d3668e">XV_HdmiTx1::StreamUpRef</a>, <a class="el" href="xv__hdmitx1_8c.html#a1b7d74b3288271064644bda7857a1c8b">XV_HdmiTx1_AuxEnable()</a>, <a class="el" href="xv__hdmitx1_8h.html#aeefc5a50cd7f61f65466eec26592b3c4">XV_HdmiTx1_AuxIntrEnable</a>, <a class="el" href="xv__hdmitx1_8h.html#ae2165f794a177f55510c8352ecc9a98b">XV_HdmiTx1_DynHdr_DM_Enable</a>, and <a class="el" href="xv__hdmitx1_8h.html#adffdae706dbe4333e7f81664ccf0fd22">XV_HdmiTx1_SetFrlActive()</a>.</p>

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          <td class="memname">int XV_HdmiTx1_FrlStreamStop </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function stops FRL video stream. </p>
<p>This should be called after the bridge, video, audio are all active.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a59d80fb969eedd5ca7c59960fe5460a7">XV_HdmiTx1_Stream::State</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a4929690dcb3684990ea7cb5d2f6cb497">XV_HdmiTx1::StreamDownCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a29e2afefacc7fffc29d308d28eaa6cba">XV_HdmiTx1::StreamDownRef</a>, <a class="el" href="xv__hdmitx1_8h.html#a885cea7ad25eb7470e839cbe329b8ec4">XV_HdmiTx1_AuxDisable</a>, <a class="el" href="xv__hdmitx1_8h.html#a0c8aaaa8fc3e83d9bbfb3cfd4c32cae0">XV_HdmiTx1_AuxIntrDisable</a>, and <a class="el" href="xv__hdmitx1_8h.html#a18b2a682a5a6928c3cdee2456563227c">XV_HdmiTx1_DynHdr_DM_Disable</a>.</p>

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          <td class="memname">int XV_HdmiTx1_FrlTrainingInit </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function initializes FRL peripheral and sink's SCDC for FRL Training. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#aeb7e0c79ea8b44c2eac37ce9a063587e">XV_HdmiTx1_Stream::Frl</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#adfeeedbdb9a0a9c4a7ecc2d7b21f3704">XV_HdmiTx1_Frl::FrlRate</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="xv__hdmitx1_8c.html#ab9b6a97a3396e177e52f69f6b5d88123">XV_HdmiTx1_DdcWriteField()</a>, <a class="el" href="xv__hdmitx1_8h.html#a552e68759230c18b75c2d5510b556488">XV_HdmiTx1_FrlModeEn()</a>, <a class="el" href="xv__hdmitx1_8h.html#ad03f1110009425d476e007abd30898d6">XV_HdmiTx1_FrlRate()</a>, and <a class="el" href="xv__hdmitx1_8h.html#adffdae706dbe4333e7f81664ccf0fd22">XV_HdmiTx1_SetFrlActive()</a>.</p>

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          <td class="memname">XV_HdmiTx1_AudioFormatType XV_HdmiTx1_GetAudioFormat </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function gets the active audio format. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Active audio format of HDMI Tx</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a52b9186ae2de6f7846338a83b0d7047f">XV_HDMITX1_AUD_CTRL_3DAUDFMT_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a93c2f397d3ac840e116f0d2d9dd74262">XV_HDMITX1_AUD_CTRL_AUDFMT_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ac103acef218d3189d2317c829c70e60e">XV_HDMITX1_AUD_CTRL_AUDFMT_SHIFT</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a5c80837a1f240f83e131771e1180bf32">XV_HDMITX1_AUD_CTRL_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>.</p>

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          <td class="memname">u32 XV_HdmiTx1_GetFrlTimer </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function returns the remaining value of the timer of TX Core's FRL peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Remaining value of the timer in clock cycles.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a1af817a6e8f37b0a75cf466dd7b2e5c2">XV_HDMITX1_FRL_TMR_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>.</p>

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          <td class="memname">u8* XV_HdmiTx1_GetScdcEdRegisters </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function reads the CED and RSED registers from the sink and returns the pointer to the data structure which stores the CED related readings (from SCDC register 0x50 to 0x5A). </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Reading the SCDC registers will clear the values at the sink </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a94632fdfed2327f40f06b80162ae6244">XV_HdmiTx1_Stream::ScdcEd</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, and <a class="el" href="xv__hdmitx1_8c.html#a9a71a92b44c225aa265a3c5852971df7">XV_HdmiTx1_DdcReadReg()</a>.</p>

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          <td class="memname">u64 XV_HdmiTx1_GetTmdsClk </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function sets and return the TMDS Clock based on Video Parameter from the InstancePtr. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TMDS Clock</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a9516babecbb4fd2a295df625a12473d5">XV_HdmiTx1_Stream::PixelClk</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, and <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a294dfd0caf934682685fafc257d49e2b">XV_HdmiTx1_Stream::Video</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a7a20221c997a381a61b4e7e98c5a4370">XV_HdmiTx1_SetStream()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_Info </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function prints stream and timing information on STDIO/Uart console. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, and <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a294dfd0caf934682685fafc257d49e2b">XV_HdmiTx1_Stream::Video</a>.</p>

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          <td class="memname">void XV_HdmiTx1_INT_LRST </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Reset</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function asserts or releases the HDMI TX Internal LRST. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">Reset</td><td>specifies TRUE/FALSE value to either assert or release HDMI TX Internal LRST.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI TX. Therefore, clearing the PIO reset output will assert the HDMI Internal link reset. C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#adf9e5c73a5f308d04eea85dd4db8f42f" title="This function asserts or releases the HDMI TX Internal VRST. ">XV_HdmiTx1_INT_VRST(XV_HdmiTx1 *InstancePtr, u8 Reset)</a> </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ae926811c3ab955754b7e1d34e06c0b30">XV_HDMITX1_PIO_OUT_INT_LRST_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiTx1_INT_VRST </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Reset</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function asserts or releases the HDMI TX Internal VRST. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">Reset</td><td>specifies TRUE/FALSE value to either assert or release HDMI TX Internal VRST.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>The reset output of the PIO is inverted. When the system is in reset, the PIO output is cleared and this will reset the HDMI TX. Therefore, clearing the PIO reset output will assert the HDMI Internal video reset. C-style signature: void <a class="el" href="xv__hdmitx1_8h.html#adf9e5c73a5f308d04eea85dd4db8f42f" title="This function asserts or releases the HDMI TX Internal VRST. ">XV_HdmiTx1_INT_VRST(XV_HdmiTx1 *InstancePtr, u8 Reset)</a> </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a34819a1c42353de5eec449bc38c93efc">XV_HDMITX1_PIO_OUT_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#abb0a513439f7691a66e0baba33ee7e99">XV_HDMITX1_PIO_OUT_INT_VRST_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiTx1_IntrHandler </td>
          <td>(</td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function is the interrupt handler for the HDMI TX driver. </p>
<p>This handler reads the pending interrupt from PIO and DDC peripheral, determines the source of the interrupts, clears the interrupts and calls callbacks accordingly.</p>
<p>The application is responsible for connecting this function to the interrupt system. Application beyond this driver is also responsible for providing callbacks to handle interrupts and installing the callbacks using <a class="el" href="xv__hdmitx1_8h.html#ab5ebe4123d67f311237f44d4db7fbb99" title="This function installs an asynchronous callback function for the given HandlerType: ...">XV_HdmiTx1_SetCallback()</a> during initialization phase. An example delivered with this driver demonstrates how this could be done.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> instance that just interrupted.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___config.html#ac9448a4fb60f4bf571da4e1c49bf0056">XV_HdmiTx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#abc4e2c7cd581d8e407d845f1a620d3d8">XV_HdmiTx1::IsReady</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a7add990341b3e99c486abdb4e730c5e2">XV_HDMITX1_AUX_STA_IRQ_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a14dcc9b57dc6ff4a5d43c9df86e54723">XV_HDMITX1_AUX_STA_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a74458333d15b366f123b04bb3fa44042">XV_HDMITX1_DDC_STA_IRQ_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a76a8d1762bfc7aafed3ae667630f47d6">XV_HDMITX1_DDC_STA_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ad6246682008ba157f08ac24f80294eed">XV_HDMITX1_FRL_STA_IRQ_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#af69097b14c333e4e03d8934c68e5666a">XV_HDMITX1_FRL_STA_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ab68b9045690c17f85d3d454f182aaaa4">XV_HDMITX1_PIO_STA_IRQ_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#aad716fe9cadcb6ad07df46c18b0f67d9">XV_HDMITX1_PIO_STA_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>.</p>

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          <td class="memname">int XV_HdmiTx1_IsStreamConnected </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function provides the stream connected status. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE = Stream is connected.</li>
<li>FALSE = Stream is connected.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#afa7e042159e99edf7f02139af8cba046">XV_HdmiTx1_Stream::IsConnected</a>, and <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>.</p>

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          <td class="memname">int XV_HdmiTx1_IsStreamScrambled </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function provides status of the stream. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE = Scrambled.</li>
<li>FALSE = Not scrambled.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a195ea9a4cc60940fab80604ebb6a2651">XV_HdmiTx1_Stream::IsScrambled</a>, and <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>.</p>

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          <td class="memname"><a class="el" href="struct_x_v___hdmi_tx1___config.html">XV_HdmiTx1_Config</a>* XV_HdmiTx1_LookupConfig </td>
          <td>(</td>
          <td class="paramtype">u16&#160;</td>
          <td class="paramname"><em>DeviceId</em></td><td>)</td>
          <td></td>
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<p>This function returns a reference to an <a class="el" href="struct_x_v___hdmi_tx1___config.html" title="This typedef contains configuration information for the HDMI TX core. ">XV_HdmiTx1_Config</a> structure based on the core id, <em>DeviceId</em>. </p>
<p>The return value will refer to an entry in the device configuration table defined in the xv_hdmitx1_g.c file.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DeviceId</td><td>is the unique core ID of the HDMI TX core for the lookup operation.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>XV_HdmiTx1_LookupConfig returns a reference to a config record in the configuration table (in xv_hdmitx1_g.c) corresponding to <em>DeviceId</em>, or NULL if no match is found.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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          <td class="memname">u8 XV_HdmiTx1_LookupVic </td>
          <td>(</td>
          <td class="paramtype">XVidC_VideoMode&#160;</td>
          <td class="paramname"><em>VideoMode</em></td><td>)</td>
          <td></td>
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<p>This function provides video identification code of video mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">VideoMode</td><td>specifies resolution identifier.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Video identification code defined in the VIC table.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

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          <td class="memname">void XV_HdmiTx1_RegisterDebug </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function prints out HDMI TX register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___config.html#ac9448a4fb60f4bf571da4e1c49bf0056">XV_HdmiTx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a91a37eb1ef5f54705a9643b9ff7c8797">XV_HDMITX1_FRL_FEC_ERR_INJ_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>.</p>

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          <td class="memname">int XV_HdmiTx1_Scrambler </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function controls the scrambler. </p>
<p>Requires TMDSClock to be up to date in order to force enable scrambler when TMDSClock &gt; 340MHz.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if HDMI 2.0</li>
<li>XST_FAILURE if HDMI 1.4</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a195ea9a4cc60940fab80604ebb6a2651">XV_HdmiTx1_Stream::IsScrambled</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a9947243bcf378409927347939617a886">XV_HdmiTx1_Stream::OverrideScrambler</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a4cee4a4b0708d7e886ab923114753d75">XV_HdmiTx1_Stream::ScdcSupport</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a07e8f7fff100be805de99a80219c2f8c">XV_HdmiTx1_Stream::TMDSClock</a>, <a class="el" href="xv__hdmitx1_8c.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, <a class="el" href="xv__hdmitx1_8c.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a669f967b9baf869d60aa8dc35297ee3a">XV_HdmiTx1_SetScrambler</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a7a20221c997a381a61b4e7e98c5a4370">XV_HdmiTx1_SetStream()</a>.</p>

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          <td class="memname">int XV_HdmiTx1_SelfTest </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function reads ID of HDMI TX PIO peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if PIO ID was matched.</li>
<li>XST_FAILURE if PIO ID was mismatched.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___config.html#ac9448a4fb60f4bf571da4e1c49bf0056">XV_HdmiTx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a02751a20bad34eb921ded41ecd6449bd">XV_HDMITX1_MASK_16</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a85275d4df3edf2c08d38d544b5928c95">XV_HDMITX1_PIO_ID</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a771c245a4146fa673670d145a49ab42c">XV_HDMITX1_PIO_ID_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#a52b7d366cc179f1aa90b20ae9ed5a6de">XV_HDMITX1_SHIFT_16</a>.</p>

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          <td class="memname">int XV_HdmiTx1_SetAudioChannels </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Value</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>This function sets the active audio channels. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if active channels were set.</li>
<li>XST_FAILURE if no active channles were set.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a07040ad23704877ed3f55d8f25456b95">XV_HDMITX1_3DAUD_CTRL_CH_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a73acb585d91a8a036c65d832a7ff030d">XV_HDMITX1_3DAUD_CTRL_CH_SHIFT</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a29066f63afe9beeadac7a04ef1fecb3b">XV_HDMITX1_AUD_CTRL_CH_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a091a4a9dacc2d0fd8f881d5b6486f11e">XV_HDMITX1_AUD_CTRL_CH_SHIFT</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a279874e2cee1de19fee34f5f25fe4198">XV_HDMITX1_AUD_CTRL_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a5c80837a1f240f83e131771e1180bf32">XV_HDMITX1_AUD_CTRL_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a0b6ca194e0811b7201545d206d1a49e3">XV_HDMITX1_AUD_CTRL_RUN_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ac630a1dbb83be6d4e64757a3d09c2cc0">XV_HDMITX1_AUD_CTRL_SET_OFFSET</a>, <a class="el" href="xv__hdmitx1_8c.html#ae842f2e11b05dbc07382f202bffbf7ea">XV_HdmiTx1_AudioEnable()</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XV_HdmiTx1_AudioFormatType&#160;</td>
          <td class="paramname"><em>Value</em>&#160;</td>
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          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function sets the active audio format. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if active channels were set.</li>
<li>XST_FAILURE if no active channles were set.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a7098260b81b3a81f1325d55f3fc5e25a">XV_HDMITX1_AUD_CTRL_3DAUDFMT_EN</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a52b9186ae2de6f7846338a83b0d7047f">XV_HDMITX1_AUD_CTRL_3DAUDFMT_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a93c2f397d3ac840e116f0d2d9dd74262">XV_HDMITX1_AUD_CTRL_AUDFMT_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a279874e2cee1de19fee34f5f25fe4198">XV_HDMITX1_AUD_CTRL_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a5c80837a1f240f83e131771e1180bf32">XV_HDMITX1_AUD_CTRL_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a0b6ca194e0811b7201545d206d1a49e3">XV_HDMITX1_AUD_CTRL_RUN_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ac630a1dbb83be6d4e64757a3d09c2cc0">XV_HDMITX1_AUD_CTRL_SET_OFFSET</a>, <a class="el" href="xv__hdmitx1_8c.html#ae842f2e11b05dbc07382f202bffbf7ea">XV_HdmiTx1_AudioEnable()</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetAxiClkFreq </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>ClkFreq</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets the AXI4-Lite Clock Frequency. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">ClkFreq</td><td>specifies the value that needs to be set.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>This is required after a reset or init. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#aed733a651634b05b6113daf320c32646">XV_HdmiTx1::CpuClkFreq</a>, and <a class="el" href="xv__hdmitx1_8c.html#a0304469fda5cb9070c1c0db0c229f11c">XV_HdmiTx1_DdcInit()</a>.</p>

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          <td class="memname">int XV_HdmiTx1_SetCallback </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="xv__hdmitx1_8h.html#af9b30d0cba10a37e4719114fe400ea64">XV_HdmiTx1_HandlerType</a>&#160;</td>
          <td class="paramname"><em>HandlerType</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallbackFunc</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">void *&#160;</td>
          <td class="paramname"><em>CallbackRef</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function installs an asynchronous callback function for the given HandlerType: </p>
<pre>
HandlerType              Callback Function Type
-----------------------  --------------------------------------------------
(XV_HDMITX1_HANDLER_HPD)   HpdCallback
(XV_HDMITX1_HANDLER_VS)    VsCallback
</pre><dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the HDMI TX core instance. </td></tr>
    <tr><td class="paramname">HandlerType</td><td>specifies the type of handler. </td></tr>
    <tr><td class="paramname">CallbackFunc</td><td>is the address of the callback function. </td></tr>
    <tr><td class="paramname">CallbackRef</td><td>is a user data item that will be passed to the callback function when it is invoked.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if callback function installed successfully.</li>
<li>XST_INVALID_PARAM when HandlerType is invalid.</li>
</ul>
</dd></dl>
<dl class="section note"><dt>Note</dt><dd>Invoking this function for a handler that already has been installed replaces it with the new handler. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1.html#a1f62d35265c8e9575806e96d5dff4b5a">XV_HdmiTx1::BrdgLockedCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#add4ef24bbf855bdb99cbc895f3728080">XV_HdmiTx1::BrdgLockedRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a5ee28de741dedce0c80df05efc6b4393">XV_HdmiTx1::BrdgOverflowCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a93b678d829092eb3df9320b2e4e8872a">XV_HdmiTx1::BrdgOverflowRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8d72f931c95c5dd096a95792dc005a2a">XV_HdmiTx1::BrdgUnderflowCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a72aa05a028a053c769c88887279c84c1">XV_HdmiTx1::BrdgUnderflowRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a41128322a34d6f217ffac92670003c9e">XV_HdmiTx1::BrdgUnlockedCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a070e92ea218d1165fda851951553b35a">XV_HdmiTx1::BrdgUnlockedRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a88195ea134a8be086cca6156bd5d87df">XV_HdmiTx1::CedUpdateCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a9bf336d986341f807a93dd7aa12d457f">XV_HdmiTx1::CedUpdateRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#aef6b3f6753d278df67f1c9803f667e08">XV_HdmiTx1::ConnectCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a99c1d407019995c9faedf34060140f35">XV_HdmiTx1::ConnectRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a2b619bbff33578107cf420cacecd2e18">XV_HdmiTx1::DscDecodeFailCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#ac635278b5e2faa35578d29830359877a">XV_HdmiTx1::DscDecodeFailRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#aa75eb56d2fcf4058da44bb2a2c3eba9b">XV_HdmiTx1::DynHdrMtwCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a027b1a92f27a2b2839254e3a69120fd1">XV_HdmiTx1::DynHdrMtwRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#ac495d5b8980b11427969918c7ea6eb56">XV_HdmiTx1::FrlConfigCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a26e0379b6c6b94faae7e5c52aec5e73e">XV_HdmiTx1::FrlConfigRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#ada61680a6092bdfeb4057cbd70e07584">XV_HdmiTx1::FrlFfeCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a23e3de569323bfc387f1f9e97f409fc1">XV_HdmiTx1::FrlFfeRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a9c4f784b98baa848eaba0f184e4f6cf8">XV_HdmiTx1::FrlLts1Callback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a7f5ad8e61c677bc4ac96e9673bde9e0d">XV_HdmiTx1::FrlLts1Ref</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a77f9f144ed1b1f0f406bbb8c671b0de3">XV_HdmiTx1::FrlLts2Callback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#ae463ce8fdabc072cd2200d87f5840900">XV_HdmiTx1::FrlLts2Ref</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a54f7b221e53ad112c54f2ef2ab77483a">XV_HdmiTx1::FrlLts3Callback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a7c82198d3afb1e336b5866f9a538cbda">XV_HdmiTx1::FrlLts3Ref</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#ab984cfb1fd3a88d5478b399a0e5ea2ea">XV_HdmiTx1::FrlLts4Callback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#aa5ebb5f0ac5d8311b724bc7c979f909a">XV_HdmiTx1::FrlLts4Ref</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a77650863384c1b134f3e8a26bb195d50">XV_HdmiTx1::FrlLtsLCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a78b99d681974d6fc18685eef62edad06">XV_HdmiTx1::FrlLtsLRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a346dde9dc2fb73ea526587978c14f493">XV_HdmiTx1::FrlLtsPCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#ac113465b484ed544caa647b3df1cf578">XV_HdmiTx1::FrlLtsPRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a4a76a4f44c11da6514bfcd2b366ee79a">XV_HdmiTx1::FrlStartCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a3676bc4ca72e0c3ac3695124574aa812">XV_HdmiTx1::FrlStartRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#abc1b2a59bc184f8461952572773a3b1d">XV_HdmiTx1::FrlStopCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a3e2dd2bf272b13923b08e8a811bdef8c">XV_HdmiTx1::FrlStopRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a4929690dcb3684990ea7cb5d2f6cb497">XV_HdmiTx1::StreamDownCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a29e2afefacc7fffc29d308d28eaa6cba">XV_HdmiTx1::StreamDownRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a01870b62d198af5f708b320a2339f9d3">XV_HdmiTx1::StreamUpCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#ac371f98870269cb29be2e43d48d3668e">XV_HdmiTx1::StreamUpRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a7be7f63d8a5bd9f54b4e186dc82820bc">XV_HdmiTx1::TmdsConfigCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#adf9d9f60674222a643f9ad7f0c8e4187">XV_HdmiTx1::TmdsConfigRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#af48a03329a29f3358af6bc289f510797">XV_HdmiTx1::ToggleCallback</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#ac0d8301d7b26b1c99874123b07e6be46">XV_HdmiTx1::ToggleRef</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a529cf861436423034baa776592647e3e">XV_HdmiTx1::VsCallback</a>, and <a class="el" href="struct_x_v___hdmi_tx1.html#a12a90e7a33dd7c9ca21603f82912b73d">XV_HdmiTx1::VsRef</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetColorDepth </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This function sets the color depth. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___config.html#ac9448a4fb60f4bf571da4e1c49bf0056">XV_HdmiTx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a294dfd0caf934682685fafc257d49e2b">XV_HdmiTx1_Stream::Video</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a58610b772b050b3a4504d274bd53f09a">XV_HDMITX1_PIO_OUT_COLOR_DEPTH_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a9044e4c1c1a22e9f5540b3e28e164ebe">XV_HDMITX1_PIO_OUT_COLOR_DEPTH_SHIFT</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ae9de0ab9551b81695551dd340024f11a">XV_HDMITX1_PIO_OUT_MSK_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#aef14faec6d7dec76359597de87c027e1">XV_HDMITX1_PIO_OUT_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a7a20221c997a381a61b4e7e98c5a4370">XV_HdmiTx1_SetStream()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetColorFormat </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function sets the color format. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___config.html#ac9448a4fb60f4bf571da4e1c49bf0056">XV_HdmiTx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a294dfd0caf934682685fafc257d49e2b">XV_HdmiTx1_Stream::Video</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ac9a6bae49a6bba1d495a19e74aff47d8">XV_HDMITX1_PIO_OUT_COLOR_SPACE_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#aef681ccbd7dad5067f84ef4b7ecdc685">XV_HDMITX1_PIO_OUT_COLOR_SPACE_SHIFT</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ae9de0ab9551b81695551dd340024f11a">XV_HDMITX1_PIO_OUT_MSK_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#aef14faec6d7dec76359597de87c027e1">XV_HDMITX1_PIO_OUT_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a7a20221c997a381a61b4e7e98c5a4370">XV_HdmiTx1_SetStream()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetDviMode </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function sets the core into DVI mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>This is required after a reset or init. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="xv__hdmitx1_8h.html#ac80822fe192ddd125e321cdf4c9d4608">XV_HdmiTx1_AudioDisable</a>, <a class="el" href="xv__hdmitx1_8h.html#a885cea7ad25eb7470e839cbe329b8ec4">XV_HdmiTx1_AuxDisable</a>, and <a class="el" href="xv__hdmitx1_8h.html#a4ed1526a4760bbcb4b978ff021fbc360">XV_HdmiTx1_ClearMode</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetFrl10MicroSecondsTimer </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function sets the timer of TX Core's FRL peripheral for 10 Microseconds. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance.</td></tr>
    <tr><td class="paramname">None.</td><td></td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a1af817a6e8f37b0a75cf466dd7b2e5c2">XV_HDMITX1_FRL_TMR_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#aed13a9750e5630a68e868533846cd0f3">XV_HdmiTx1_StartTmdsMode()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetFrlActive </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XV_HdmiTx1_FrlActiveMode&#160;</td>
          <td class="paramname"><em>Mode</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets active FRL mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
    <tr><td class="paramname">Mode</td><td>specifies the active FRL mode.<ul>
<li>0 = FRL transmission only includes GAP characters</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<ul>
<li>1 = FRL transmission includes video, audio and control packets</li>
</ul>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a4106f7902fe789c40042b05956e9ee39">XV_HDMITX1_FRL_ACT_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#aa5da06390a2ac2dc17a7581c3cc7f81a">XV_HDMITX1_FRL_CTRL_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ae76270b448224670d8cd9615dbac2091">XV_HDMITX1_FRL_CTRL_SET_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a86472ba3e4497749a3b0af4fd446137d">XV_HdmiTx1_FrlStreamStart()</a>, and <a class="el" href="xv__hdmitx1_8h.html#a730bc782f3ed005fbff8e45c1dbd055a">XV_HdmiTx1_FrlTrainingInit()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetFrlLanes </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Lanes</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
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<p>This function sets the number of FRL lane in operations. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
    <tr><td class="paramname">Lanes</td><td>specifies the number of FRL lanes in operation.<ul>
<li>3 = 3 FRL lanes</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<ul>
<li>4 = 4 FRL lanes</li>
</ul>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#aa5da06390a2ac2dc17a7581c3cc7f81a">XV_HDMITX1_FRL_CTRL_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a5fe062b0a3114ac13ab10e99fd02dcd3">XV_HDMITX1_FRL_CTRL_LN_OP_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ae76270b448224670d8cd9615dbac2091">XV_HDMITX1_FRL_CTRL_SET_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ad03f1110009425d476e007abd30898d6">XV_HdmiTx1_FrlRate()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetFrlLtp </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>Lane</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XV_HdmiTx1_FrlLtpType&#160;</td>
          <td class="paramname"><em>Ltp</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets the link training pattern for the selected lane. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
    <tr><td class="paramname">Lane</td><td>specifies the lane of which the Link Training Pattern will be set.</td></tr>
    <tr><td class="paramname">Ltp</td><td>specifies Link Training Pattern<ul>
<li>0 = No LTP</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<ul>
<li>1 = LTP1 / ALL 1's pattern</li>
<li>2 = LTP2 / All 0's pattern</li>
<li>3 = LTP3 / Nyquist clock pattern</li>
<li>4 = LTP4 / Source TxDDE compliance test pattern</li>
<li>5 = LTP5 / LFSR 0</li>
<li>6 = LTP6 / LFSR 1</li>
<li>7 = LTP7 / LFSR 2</li>
<li>8 = LTP8 / LFSR 3</li>
</ul>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#abc06f99f814e758f194f5afab57fd7e1">XV_HDMITX1_FRL_CTRL_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a7505796b81e52d346f14abb3b1a24bfa">XV_HDMITX1_FRL_LTP0_REQ_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a53c5fc702ac87b8400ece0a29d50177b">XV_HDMITX1_FRL_LTP0_REQ_SHIFT</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a232c20ed50d25e04f96b918341d9855d">XV_HDMITX1_FRL_LTP1_REQ_SHIFT</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a97e4f75036407536b66c397d45f641af">XV_HDMITX1_FRL_LTP2_REQ_SHIFT</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a8809fb1d8b55f999acb54a84945598d2">XV_HDMITX1_FRL_LTP3_REQ_SHIFT</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetFrlMaxFrlRate </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XHdmiC_MaxFrlRate&#160;</td>
          <td class="paramname"><em>MaxFrlRate</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets maximum FRL Rate supported by the system. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
    <tr><td class="paramname">MaxFrlRate</td><td>specifies maximum rates supported<ul>
<li>0 = FRL Not Supported</li>
<li>1 = 3 Lanes 3Gbps</li>
<li>2 = 4 Lanes 3Gbps</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<ul>
<li>3 = 4 Lanes 6Gbsp</li>
<li>4 = 4 Lanes 8Gbps</li>
<li>5 = 4 Lanes 10Gbps</li>
<li>6 = 4 Lanes 12Gbps</li>
</ul>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#aeb7e0c79ea8b44c2eac37ce9a063587e">XV_HdmiTx1_Stream::Frl</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#a7ae9e5018c441354a23323082dc6aa76">XV_HdmiTx1_Frl::MaxFrlRate</a>, <a class="el" href="struct_x_v___hdmi_tx1___config.html#a7f80ad7a8e8dd3c68792fcda5196f74a">XV_HdmiTx1_Config::MaxFrlRate</a>, and <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetFrlTimer </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Milliseconds</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets the timer of TX Core's FRL peripheral. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance.</td></tr>
    <tr><td class="paramname">Value</td><td>specifies the timer's frequency (in milliseconds)</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a1af817a6e8f37b0a75cf466dd7b2e5c2">XV_HDMITX1_FRL_TMR_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetFrlTimerClockCycles </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>ClockCycles</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets the timer of TX Core's FRL peripheral in clock cycles. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance.</td></tr>
    <tr><td class="paramname">ClockCycles</td><td>specifies the timer's frequency (in clock cycles)</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Remaining value of the timer in clock cycles.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a1af817a6e8f37b0a75cf466dd7b2e5c2">XV_HDMITX1_FRL_TMR_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, and <a class="el" href="xv__hdmitx1_8h.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetFrlWrongLtp </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function sets the core to send out wrong LTP on one of the channel to prevent link training from passing. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XHdmi_Tx core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#aeb7e0c79ea8b44c2eac37ce9a063587e">XV_HdmiTx1_Stream::Frl</a>, and <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetGcpAvmuteBit </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function sets the HDMI TX AUX GCP register AVMUTE bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#acdf644126236c17fe0561f8b7b35e848">XV_HDMITX1_PIO_OUT_GCP_AVMUTE_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetGcpClearAvmuteBit </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function sets the HDMI TX AUX GCP register CLEAR_AVMUTE bit. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#af12c5bc4580008e386420488c4dc2945">XV_HDMITX1_PIO_OUT_GCP_CLEARAVMUTE_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a916d49f0a22d9ef6e369ff80353e00af">XV_HDMITX1_PIO_OUT_SET_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetHdmiFrlMode </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function sets the core into HDMI FRL mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>This is required after a reset or init. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="xv__hdmitx1_8c.html#ae842f2e11b05dbc07382f202bffbf7ea">XV_HdmiTx1_AudioEnable()</a>, <a class="el" href="xv__hdmitx1_8c.html#a1b7d74b3288271064644bda7857a1c8b">XV_HdmiTx1_AuxEnable()</a>, and <a class="el" href="xv__hdmitx1_8h.html#af3a6c361d3eb8f9bc43cc1d4f6bc2269">XV_HdmiTx1_SetMode</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetHdmiTmdsMode </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
      </table>
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<p>This function sets the core into HDMI TMDS mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<dl class="section note"><dt>Note</dt><dd>This is required after a reset or init. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="xv__hdmitx1_8c.html#ae842f2e11b05dbc07382f202bffbf7ea">XV_HdmiTx1_AudioEnable()</a>, <a class="el" href="xv__hdmitx1_8c.html#a1b7d74b3288271064644bda7857a1c8b">XV_HdmiTx1_AuxEnable()</a>, and <a class="el" href="xv__hdmitx1_8h.html#af3a6c361d3eb8f9bc43cc1d4f6bc2269">XV_HdmiTx1_SetMode</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ade49d67af0d4ac0c3d5756a5cfdfe15f">XV_HdmiTx1_CfgInitialize()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetPixelRate </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function sets the pixel rate at output. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___config.html#ac9448a4fb60f4bf571da4e1c49bf0056">XV_HdmiTx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a7fa66e3baa8894a6c59b3fbc96d18354">XV_HdmiTx1_Stream::CorePixPerClk</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ae9de0ab9551b81695551dd340024f11a">XV_HDMITX1_PIO_OUT_MSK_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#aef14faec6d7dec76359597de87c027e1">XV_HDMITX1_PIO_OUT_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a493cc4bcc9456c6e4b5b7b6f4ef278c7">XV_HDMITX1_PIO_OUT_PIXEL_RATE_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a6fe7c0047c787b5b463931d65a9857aa">XV_HDMITX1_PIO_OUT_PIXEL_RATE_SHIFT</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#a7a20221c997a381a61b4e7e98c5a4370">XV_HdmiTx1_SetStream()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_SetSampleRate </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>SampleRate</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function sets the sample rate at output. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">SampleRate</td><td>specifies the value that needs to be set.<ul>
<li>2 samples per clock</li>
<li>3 samples per clock.</li>
<li>5 samples per clock.</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___config.html#ac9448a4fb60f4bf571da4e1c49bf0056">XV_HdmiTx1_Config::BaseAddress</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a821b6ed4f07983491f150fb061ba224e">XV_HdmiTx1::Config</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#aa3aac13005a54f8b27d42bf9c3f4b17d">XV_HdmiTx1_Stream::SampleRate</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ae9de0ab9551b81695551dd340024f11a">XV_HDMITX1_PIO_OUT_MSK_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#aef14faec6d7dec76359597de87c027e1">XV_HDMITX1_PIO_OUT_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a36e3a208b0ef9f5385c89a994916c49c">XV_HDMITX1_PIO_OUT_SAMPLE_RATE_MASK</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ab23dda9e51f0e85b00f859790bce3ad4">XV_HDMITX1_PIO_OUT_SAMPLE_RATE_SHIFT</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

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          <td class="memname">u32 XV_HdmiTx1_SetStream </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XVidC_VideoTiming&#160;</td>
          <td class="paramname"><em>VideoTiming</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XVidC_FrameRate&#160;</td>
          <td class="paramname"><em>FrameRate</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XVidC_ColorFormat&#160;</td>
          <td class="paramname"><em>ColorFormat</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XVidC_ColorDepth&#160;</td>
          <td class="paramname"><em>Bpc</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XVidC_PixelsPerClock&#160;</td>
          <td class="paramname"><em>Ppc</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XVidC_3DInfo *&#160;</td>
          <td class="paramname"><em>Info3D</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>FVaFactor</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>VrrEnabled</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>CnmvrrEnabled</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u64 *&#160;</td>
          <td class="paramname"><em>TmdsClock</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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      </table>
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<p>This function sets the HDMI TX stream parameters. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance. </td></tr>
    <tr><td class="paramname">VideoTiming</td><td>specifies video timing. </td></tr>
    <tr><td class="paramname">FrameRate</td><td>specifies frame rate. </td></tr>
    <tr><td class="paramname">ColorFormat</td><td>specifies the type of color format.<ul>
<li>0 = XVIDC_CSF_RGB</li>
<li>1 = XVIDC_CSF_YCRCB_444</li>
<li>2 = XVIDC_CSF_YCRCB_422</li>
<li>3 = XVIDC_CSF_YCRCB_420 </li>
</ul>
</td></tr>
    <tr><td class="paramname">Bpc</td><td>specifies the color depth/bits per color component.<ul>
<li>6 = XVIDC_BPC_6</li>
<li>8 = XVIDC_BPC_8</li>
<li>10 = XVIDC_BPC_10</li>
<li>12 = XVIDC_BPC_12</li>
<li>16 = XVIDC_BPC_16 </li>
</ul>
</td></tr>
    <tr><td class="paramname">Ppc</td><td>specifies the pixel per clock.<ul>
<li>4 = XVIDC_PPC_4 </li>
</ul>
</td></tr>
    <tr><td class="paramname">Info3D</td><td>3D info </td></tr>
    <tr><td class="paramname">FVaFactor</td><td>- Fast Video Active Factor </td></tr>
    <tr><td class="paramname">VrrEnabled</td><td>- VRR is enabled or not </td></tr>
    <tr><td class="paramname">CnmvrrEnabled</td><td>- Negative VRR supported flag </td></tr>
    <tr><td class="paramname">TmdsClock,reference</td><td>clock calculated based on the input parameters.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>XST_SUCCESS on success else XST_FAILURE</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>
<p>In HDMI the colordepth in YUV422 is always 12 bits, although on the link itself it is being transmitted as 8-bits. Therefore if the colorspace is YUV422, then force the colordepth to 12 bits. </p>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a195ea9a4cc60940fab80604ebb6a2651">XV_HdmiTx1_Stream::IsScrambled</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a4cee4a4b0708d7e886ab923114753d75">XV_HdmiTx1_Stream::ScdcSupport</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a07e8f7fff100be805de99a80219c2f8c">XV_HdmiTx1_Stream::TMDSClock</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#abd62e567ccef9f34c2614909fed625ce">XV_HdmiTx1_Stream::TMDSClockRatio</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a294dfd0caf934682685fafc257d49e2b">XV_HdmiTx1_Stream::Video</a>, <a class="el" href="xv__hdmitx1_8c.html#af8b34671e3735035e8dd68f6bdbb7904">XV_HdmiTx1_ClockRatio()</a>, <a class="el" href="xv__hdmitx1_8c.html#a2fdc16b8be464514b4d72ddfb947cee9">XV_HdmiTx1_GetTmdsClk()</a>, <a class="el" href="xv__hdmitx1_8c.html#a83f6939b0f5205344a276489afe45223">XV_HdmiTx1_Scrambler()</a>, <a class="el" href="xv__hdmitx1_8c.html#a25379b09e782626e79fd3b785b671f2e">XV_HdmiTx1_SetColorDepth()</a>, <a class="el" href="xv__hdmitx1_8c.html#a0aa5bbd57a95785df766d6d5a919479a">XV_HdmiTx1_SetColorFormat()</a>, and <a class="el" href="xv__hdmitx1_8c.html#a606cf8a2a1153de19c66925b9d462636">XV_HdmiTx1_SetPixelRate()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_ShowSCDC </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function shows the sinks SCDC registers. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1_8c.html#a8e431bf1d16450b478448424d81e72ea">XV_HdmiTx1_DdcRead()</a>, and <a class="el" href="xv__hdmitx1_8c.html#ab587002464f4dbfd8db9b39199bb4bdc">XV_HdmiTx1_DdcWrite()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_Start </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function starts the HDMI TX core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>This is required after a reset or initialization. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1_8h.html#aee2b7ea5870d1eb94eb90bbfe2130e50">XV_HdmiTx1_PioEnable</a>, and <a class="el" href="xv__hdmitx1_8h.html#ac1422deaecdcaa680769832bbcfaf8a7">XV_HdmiTx1_PioIntrEnable</a>.</p>

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          <td class="memname">int XV_HdmiTx1_StartFrlTraining </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">XHdmiC_MaxFrlRate&#160;</td>
          <td class="paramname"><em>FrlRate</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>This function starts the Fixed Rate Link Training. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
    <tr><td class="paramname">FrlRate</td><td>specifies the FRL rate to be attempted<ul>
<li>0 = FRL Not Supported</li>
<li>1 = 3 Lanes 3Gbps</li>
<li>2 = 4 Lanes 3Gbps</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<ul>
<li>3 = 4 Lanes 6Gbsp</li>
<li>4 = 4 Lanes 8Gbps</li>
<li>5 = 4 Lanes 10Gbps</li>
<li>6 = 4 Lanes 12Gbps</li>
</ul>
<dl class="section return"><dt>Returns</dt><dd>Status on if FrlTraining can be started or not.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#aeb7e0c79ea8b44c2eac37ce9a063587e">XV_HdmiTx1_Stream::Frl</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#adfeeedbdb9a0a9c4a7ecc2d7b21f3704">XV_HdmiTx1_Frl::FrlRate</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#ac95410542d1d4eed581f66c49e70a9bb">XV_HdmiTx1_Frl::Lanes</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#a8d9f5de0ab29699e3308bbcd372d7888">XV_HdmiTx1_Frl::LineRate</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#a7ae9e5018c441354a23323082dc6aa76">XV_HdmiTx1_Frl::MaxFrlRate</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#afb1cf1b7d51092ef7429b95a4353ab4d">XV_HdmiTx1_Frl::TrainingState</a>, and <a class="el" href="xv__hdmitx1_8h.html#adf710dcbcdbe81ecb243be229e21c5b4">XV_HdmiTx1_ExecFrlState()</a>.</p>

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          <td class="memname">int XV_HdmiTx1_StartTmdsMode </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
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<p>This function starts the TMDS mode. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Status on if TMDS can be started or not.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#aeb7e0c79ea8b44c2eac37ce9a063587e">XV_HdmiTx1_Stream::Frl</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_tx1___frl.html#afb1cf1b7d51092ef7429b95a4353ab4d">XV_HdmiTx1_Frl::TrainingState</a>, and <a class="el" href="xv__hdmitx1_8h.html#aae90d7c942d0f3c605396316c25ad28e">XV_HdmiTx1_SetFrl10MicroSecondsTimer()</a>.</p>

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          <td class="memname">void XV_HdmiTx1_Stop </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
          <td></td>
        </tr>
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<p>This function stops the HDMI TX core. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1_8h.html#adc65c495c5346d5026795fd9ae6d7cd7">XV_HdmiTx1_PioDisable</a>, and <a class="el" href="xv__hdmitx1_8h.html#a8acc56c70efc79834e9411b6cff105c5">XV_HdmiTx1_PioIntrDisable</a>.</p>

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          <td class="memname">void XV_HdmiTx1_TMDSACRStart </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function Starts the internal ACR module for FRL. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the <a class="el" href="struct_x_v___hdmi_tx1.html" title="The XV_HdmiTx1 driver instance data. ">XV_HdmiTx1</a> core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Active audio format of HDMI Tx</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="struct_x_v___hdmi_tx1___stream.html#ac110c3e0296b6f95e3647410e3ddadd2">XV_HdmiTx1_Stream::Audio</a>, <a class="el" href="struct_x_v___hdmi_tx1.html#a8812d5981337da9bcf42bd9ea41bb8ea">XV_HdmiTx1::Stream</a>, <a class="el" href="struct_x_v___hdmi_tx1___stream.html#a07e8f7fff100be805de99a80219c2f8c">XV_HdmiTx1_Stream::TMDSClock</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a07578cb7628cd825336759685d553253">XV_HDMITX1_AUD_ACR_N_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#a279874e2cee1de19fee34f5f25fe4198">XV_HDMITX1_AUD_CTRL_CLR_OFFSET</a>, <a class="el" href="xv__hdmitx1__hw_8h.html#ac630a1dbb83be6d4e64757a3d09c2cc0">XV_HDMITX1_AUD_CTRL_SET_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#af4ba16c8e4e0505aa1e7ea79d06eb2d4">XV_HdmiTx1_WriteReg</a>.</p>

<p>Referenced by <a class="el" href="xv__hdmitx1_8h.html#ae842f2e11b05dbc07382f202bffbf7ea">XV_HdmiTx1_AudioEnable()</a>.</p>

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          <td class="memname">u32 XV_HdmiTxSs1_GetAudioCtsVal </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function gets the Generated ACR CTS Value. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XV_HdmiTxSs1 core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Generated ACR CTS Value</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#adff5e5558c241deea3ea7bcd9c354a87">XV_HDMITX1_AUD_ACR_CTS_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>.</p>

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          <td class="memname">u32 XV_HdmiTxSs1_GetAudioNVal </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_x_v___hdmi_tx1.html">XV_HdmiTx1</a> *&#160;</td>
          <td class="paramname"><em>InstancePtr</em></td><td>)</td>
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<p>This function gets the programmed ACR N Value. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InstancePtr</td><td>is a pointer to the XV_HdmiTxSs1 core instance.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>Programmed ACR N Value</dd></dl>
<dl class="section note"><dt>Note</dt><dd>None. </dd></dl>

<p>References <a class="el" href="xv__hdmitx1__hw_8h.html#a07578cb7628cd825336759685d553253">XV_HDMITX1_AUD_ACR_N_OFFSET</a>, and <a class="el" href="xv__hdmitx1__hw_8h.html#a374eee1fb3e859285b0e6deeb5cd3b7b">XV_HdmiTx1_ReadReg</a>.</p>

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